Past Events

Google Cloud Seminar (Taiwan)

Join us at Google Cloud Taiwan Seminar to learn Cadence presentation on Simplifying Giga-scale Designs with EDA-optimized Cloud. You will know how Cadence Cloud is driving the future of electronic design automation and how to bridge the gap between available EDA resources and increasing complexity and size of designs.

ETHERNET & IP @ AUTOMOTIVE TECHNOLOGY DAY

Cadence is a Silver Sponsor at 2022 IEEE Ethernet and IP @ Automotive Technology Day. Cadence exhibits its Ethernet solution, which provides Automotive Ethernet MAC Design IP and Verification IP (VIP) supporting multiple speed grades from 10Mbps up to 10Gbps, including the latest Time-Sensitive Networking (TSN) standards, Ethernet rapid prototyping, and Cadence Sigrity technology for physical channel simulation. Cadence is also presenting a paper titled:“Layer 2 Security for Precision Time Protocol Frames for Automotive Ethernet”.

DesignCon 2023

Cadence is a Platinum sponsor of DesignCon—the premier high-speed communications and system design conference. Visit us in Booth 733 to see how you can improve your electromagnetic, electronic, and thermal designs with system analysis, tackle advanced IC packaging and cross-platform challenges, accelerate RF to mmWave designs, and successfully incorporate photonic ICs and designs with 112G SerDes and DDR IP.

DVCon Europe 2022

Join Matt Graham, Product Engineering Group Director, on December 6 at 4pm for his presentation on Verification 2.0 – Multi-Engine, Multi-Run – AI-Driven Verification. This talk covers some of the near-term opportunities for applying AI and ML pragmatically to verification problems and presents potential future directions for AI and ML area. Be sure to visit booth #601 to learn how Cadence is leveraging big data and AI to optimize verification productivity and efficiency with the Verisium™ platform.

DFM-Aware PCB Design Using Allegro DesignTrue DFM Technology

Join Cadence Training for this free technical Training Webinar to learn about Allegro DesignTrue DFM, which provides a range of fabrication, assembly, and test checks to ensure that your design meets manufacturing, assembly, and test requirements.

DATE 2023

The Design, Automation and Test in Europe (DATE) conference is the main European event bringing together designers and design automation users, researchers, and vendors, as well as specialists in the hardware and software design, test, and manufacturing of electronic circuits and systems. DATE puts a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems as well as embedded software.

Connect Your System Architecture Design and Implementation

The disconnect between system architecture design and implementation makes creating a system that meets cost, performance, and formfactor requirements challenging. Hardware designers need tools that help them engineer systems to meet the goals of their end products within the time-to-launch window.

CadenceTechTALK: Automate Chip Design with ML for Productivity and Performance Gains

Achieve 10X productivity and a 20% performance gain using machine learning to automate and optimize chip design. Attend this CadenceTECHTALK to hear how customers use the Cadence Cerebrus Intelligent Chip Explorer to achieve these results and more.

CadenceTECHTALK：高效模拟 IC 设计和验证的秘诀是什么？

In this CadenceTECHTALK, we will showcase the latest features of the Virtuoso ADE Product Suite. Please join in us for 1 hour free webinar

CadenceTECHTALK：电热联合仿真：提高热签核精度

Please join this free one-hour webinar to learn how to use Cadence® Celsius™ Thermal Solver

CadenceTECHTALK：如何不牺牲精度以提升模拟仿真性能

In this CadenceTECHTALK, we will show you advantages of Cadence Spectre X Simulator. Please join in us for 1 hour free webinar

CadenceTECHTALK：基于Allegro PCB 设计平台的Rigid-Flex Board Design

In this CadenceTECHTALK, we will show you advantages of Cadence Allegro PCB Designer. Please join in us for 1 hour free webinar

CadenceTECHTALK：原理图系统设计的划时代工具

In this CadenceTECHTALK, we will show you advantages of Cadence Allegro System Capture. Please join in us for 1 hour free webinar

CadenceTECHTALK：使用Common UI 数据库访问格式和脚本以提高工作效率

Please join this free one-hour webinar to learn how to use the powerful Stylus Common UI infrastructure.

CadenceTECHTALK：使用 Clarity 3D Solver进行快速简单的软硬结合板分析

Please join this free one-hour webinar to learn how to use Cadence® Clarity™ 3D Solver

CadenceTECHTALK：Via modeling and optimization

Please join this free one-hour webinar to learn Cadence High Speed Structure Optimization

CadenceTECHTALK：Fidelity AutoMesh — 极速化前处理

In this CadenceTECHTALK, we will show you advantages of Cadence Fidelity CFD software. Please join in us for 1 hour free webinar

CadenceTECHTALK：Conformal ECO：流程与方法

Please join this free one-hour webinar to learn how to use Cadence® Conformal® ECO Designer

CadenceTECHTALK:智慧系統設計新突破！以 Optimality AI 引擎 優化設計生產力(Taiwan))

本場線上研討會為各位介紹 Cadence® Optimality™ 智慧系統引擎 (Intelligent System Explorer)，不僅能協助加速產品上市並降低設計風險，透過 AI 技術探索關鍵參數，Optimality Explorer 提供的優化設計比傳統手動方法平均快 10 倍，更在某些設計上實現了高達 100 倍的加速！歡迎您加入我們 2023 年第一場線上研討會，透過專業講師的介紹與產品 demo 更深入瞭解 Cadence® Optimality™ 智慧系統引擎。 Cadence® Optimality™ Intelligent System Explorer delivers optimized designs on average 10X faster than traditional manual methods, with up to a 100X speedup realized on some designs.Register for this webinar to learn more about Cadence® Optimality™ Intelligent System Explorer.

CadenceTECHTALK:如何用 Protium企业级原型设计工具提高生产率，降低成本

Join our webinar as we identify the key requirements and challenges with prototyping, and how using enterprising prototyping systems like Cadence’s Protium system reduce the costs associated with them.

CadenceTECHTALK:使用Xcelium Logic Simulator获得最优性能

Wondering how you can easily achieve up to 3X exemplary performance gains using Xcelium Logic Simulator. This webinar provides a handy checklist of best practices covering umbrella performance switches, “access” levels, and simulation profiling to achieve the highest performance using Xcelium.

CadenceTECHTALK:Certus 突破大型晶片設計收斂與簽核時效挑戰(Taiwan)

本次線上研討會，將由Cadence 應用工程處長Jason介紹Cadence Certus 設計收斂解決方案，首創全自動化作業環境，如何同時加速設計時程及整個設計收斂週期— 從簽核優化到佈線、靜態時序分析 (STA) 和萃取，由數周縮短到一個晚上即可輕鬆完成。 Cadence Certus線上研討會即刻開放報名，歡迎加入! The Cadence Certus Closure Solution is the industry's first fully automated and massively distributed environment for full-chip optimization and signoff. Welcome to join us and learn more about this exciting new product.

CadenceTECHTALK: 提升调试效率

Verification engineers spends on an average nearly half of their time debugging, so it is no wonder that debug performance and throughput are among their top concerns. In this CadenceTECHTALK, you will learn how the Cadence® Indago™ Debug Analyzer is addressing these concerns by introducing higher performance waveform dumping, better UVM debugging capabilities, faster startup times even with large SoCs, and responsive search and driver tracing capabilities.

CadenceTECHTALK: 使用 Xcelium Simulator 简化混合信号SoC芯片验证

Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Join this webinar to learn how Cadence is providing effective verification and debug methodologies using RNM of analog blocks for mixed-signal SoC verification.

CadenceTECHTALK: 使用 Protium™ X2 加速复杂 SoC芯片原型验证

This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification.

CadenceTECHTALK: テンシリカIPセミナー

サブシステムに要求されるプリプロセッシング、AI推論、ポストプロセッシング、Always-On(AON)、レーダーなど、それぞれの処理に最適なテンシリカIPとそれらにおいて包括的にサポートされている機能安全、セキュリティ機能について、具体的なパフォーマンスや採用事例なども交えながらテンシリカIPの最新状況をご紹介します。

CadenceTECHTALK: チップ全体の最適化およびサインオフを10倍高速化するCertus Closure Solutionのご紹介

今年10月11日に発表した新製品Certus Closure Solutionを紹介いたします。並列分散同時処理によって、デザインの大きさに制限なく、タイミングおよびパワーの最適化を一晩で完了可能なソリューションの概要をユーザ事例と併せて説明いたします。

CadenceTECHTALK: Static Timing Analysis and Some Important Basics

In this webinar, we will discuss STA concepts through the definition of the basics: delays, timing checks, clocks, exceptions, etc. We will also present the way to describe and constrain these in SDC format. We finally see how SDC constraints are connected to the Cadence® Innovus™ CCOpt clock tree engine.

CadenceTECHTALK: Solutions to Detect Design Errors Early to Reduce Design Iterations

Watch this webinar recording to learn about preventing methods of signal integrity issues and how our signal integrity tool, Sigrity™ Aurora, can help you identify the ideal corrective action efficiently to solve fundamental problems.

CadenceTECHTALK: Reduce Turnaround Times with an RF/microwave Front-to-Back PCB Workflow

Workflow interoperability between the Cadence® AWR Design Environment® platform and the Allegro® PCB Design editor enables RF and layout teams to share data more efficiently, reducing design turnaround times and avoiding potential errors caused by manual entry. This webinar presents the RF-to-PCB workflow and highlights the ways in which design teams can improve productivity and time to market.

CadenceTECHTALK: Power Integrity – Tips and Tricks to Minimize PDN Noise

Join this webinar, as we explore common Power Delivery Network (PDN) problems in many designs today, and get tips and insights from our experts on resolving your Power Integrity (PI) issues before they occur.

CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation

Register for a webinar that shows how Xcelium simulation enables design verification teams to catch low-power issues very early in the verification cycle at the RTL phase with best-in-class performance and providing complete low-power coverage.

CadenceTECHTALK: Large Eddy CFD Simulation for Automotive Aerodynamics

CadenceTECHTALK: Find Elusive Bugs Faster with Xcelium ML

Register for a CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles. This webinar will cover how Xcelium simulator with the Machine Learning (ML) App improves the efficiency of your regression environment, save CPU cycles, improves bug-hunting efficiency, and speeds up coverage closure.

CadenceTECHTALK: Driving Low-Power Design with High-Level Synthesis

Discover how to drive low-power design with high-level synthesis. Join us for a webinar that shows you how to optimize your design techniques for low power while meeting performance goals. Register today.

CadenceTECHTALK: Discover Fidelity CFD Software for Faster, High-Accuracy Multiphysics Simulation

Discover how Cadence® Fidelity™ CFD Software accelerates and optimizes your design flows. Join this webinar to learn how Fidelity unites all the compelling technologies a CFD engineer needs to simulate the performance of multiphysics systems in a streamlined workflow. Fidelity offers a comprehensive suite of solutions for multiple vertical markets, including automotive, turbomachinery, marine, aerospace, and more.

CadenceTECHTALK: Digital Engineering Best Practices for Aerospace and Defense

Watch this CadenceTECHTALK™ webinar, where senior group director, solutions & ecosystems Frank Schirrmeister will discuss how commercial electronics hardware companies use cutting-edge design techniques to ensure that their hardware/software designs work as intended prior to fabrication.

CadenceTECHTALK: Applying AI/ML Technology for Rapid Design Optimization

CadenceLIVE Taiwan 2022

CadenceLIVE Taiwan 2022 will be held on September 1st at Sheraton Hsinchu Hotel. Attendees have the opportunity to attend captivating keynotes, interesting user presentations, and interact with industry leaders and Cadence experts. Register today to secure your spot.

CadenceLIVE Silicon Valley 2023

CadenceLIVE Silicon Valley brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

CadenceLIVE Silicon Valley 2022

CadenceLIVE Silicon Valley 2022 will be held on June 8-9 at the Santa Clara Convention Center. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity.

CadenceLIVE Korea 2022

CadenceLIVE Korea 2022 will be held on October 18 in Seoul. It will feature peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity.

CadenceLIVE Japan 2022

CadenceLIVE Japan 2022 will be held on July 15 at Yokohama Bay Hotel Tokyu. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

CadenceLIVE India 2022

CadenceLIVE India 2022 will be held on September 14-15 at the Radisson Blu Bengaluru Outer Ring Road Hotel in Bangalore. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

CadenceLIVE Europe 2022

CadenceLIVE Europe 2022 will be held on November 21-22 at the Park Hilton Hotel in Munich. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

CadenceLIVE China 2022

CadenceLIVE China​ 2022 brings together Cadence technology users, developers, and industry experts to connect, share ideas and best practices, and inspire design creativity.​

CadenceLIVE Boston 2022

CadenceLIVE Boston 2022 will be held on September 14 at the Boston Marriott Burlington in Burlington, MA. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

CadenceCONNECT: Verification Day

As verification tasks become more and more challenging and complexity increases, we find ourselves looking for more advanced techniques and solutions to improve and shorten this task. Come and join us at CadenceCONNECT: Verification Day to learn about the latest updates on the advanced verification solutions that include the Perspec System Verifier, System VIP, Palladium Z2 Enterprise Emulation Platform, Protium X2 Enterprise Prototyping Platform, and Jasper Formal Verification Platform.

CadenceCONNECT: Taiwan Verification Seminar

This seminar will cover, not only our latest product, Verisium AI-Driven Verification Platform, a suite of applications leveraging big data and AI to optimize verification productivity and efficiency, but many verification topics, including Xcelium Simulation, Verisium Debug Analyzer, Jasper RTL Apps, DPA for early power profiling, finally, System VIP on system verification. Come join us!

CadenceCONNECT: Photonics Contribution to High-Performance Computing

Join Cadence for the fifth annual CadenceCONNECT: Photonics Contribution for High-Performance Computing to learn from industry and academic experts how photonics can advance the next generation of HPC.