Past Events

CadenceTECHTALK：使用 Clarity 3D Solver进行快速简单的软硬结合板分析

Please join this free one-hour webinar to learn how to use Cadence® Clarity™ 3D Solver

On-Demand CadenceTECHTALK: In-Design EM Analysis Addresses RF System Integration Challenges

Watch this On-Demand CadenceTECHTALK to learn how challenges related to MMIC/RFIC integration can be identified and resolved prior to tapeout through in-design EM analysis and MMIC/RFIC co-simulation using distributed, multiprocessing EM analysis for large-scale RF structures with the Cadence’s Clarity 3D Solver and AWR Microwave Office circuit design software.

CadenceTECHTALK：Via modeling and optimization

Please join this free one-hour webinar to learn Cadence High Speed Structure Optimization

CadenceTECHTALK: チップ全体の最適化およびサインオフを10倍高速化するCertus Closure Solutionのご紹介

今年10月11日に発表した新製品Certus Closure Solutionを紹介いたします。並列分散同時処理によって、デザインの大きさに制限なく、タイミングおよびパワーの最適化を一晩で完了可能なソリューションの概要をユーザ事例と併せて説明いたします。

On-Demand CadenceTECHTALK: From MATLAB to Optimized RTL in Minutes

Learn how industry’s first integration of Stratus High Level Synthesis and MATLA shortens design schedules and delivers designs with superior PPA. This technical webinar discusses the integration in detail and features a demonstration of the technology applied to a real-world design.

CadenceTECHTALK：如何不牺牲精度以提升模拟仿真性能

In this CadenceTECHTALK, we will show you advantages of Cadence Spectre X Simulator. Please join in us for 1 hour free webinar

On-Demand CadenceTECHTALK: Integrated Thermal Analysis for RF MMIC and PCB Power Applications

Learn how you can access electrothermal analysis for your monolithic microwave IC (MMIC)/RFIC, PCB, and module designs. Watch this webinar and see how the Cadence Celsius Thermal Solver uses design data such as layout geometries, material properties, and dissipated power simulation results from Microwave Office software to provide a thermal heat map visualization and operating temperature information.

CadenceTECHTALK：电热联合仿真：提高热签核精度

Please join this free one-hour webinar to learn how to use Cadence® Celsius™ Thermal Solver

CadenceTECHTALK: テンシリカIPセミナー

サブシステムに要求されるプリプロセッシング、AI推論、ポストプロセッシング、Always-On(AON)、レーダーなど、それぞれの処理に最適なテンシリカIPとそれらにおいて包括的にサポートされている機能安全、セキュリティ機能について、具体的なパフォーマンスや採用事例なども交えながらテンシリカIPの最新状況をご紹介します。

On-Demand CadenceTECHTALK: Find more Bugs, Hit the Most Difficult Scenarios Faster

Watch this CadenceTECHTALK™, where we discuss how technologies used to improve performance, face challenges such as failing to hit new coverage, inability to identify new bugs, or help increase coverage.

On-Demand CadenceTECHTALK: Xcelium Apps: Everything You Need in the Simulation Metaverse

This CadenceTECHTALK provides an overview of the entire portfolio of Xcelium Apps, including Machine Learning, Mixed Signal, Multi-Core, Safety Verification, Power Playback, and X-Pessimism Removal. Users will learn how to seamlessly mix and match the natively integrated Xcelium Apps to achieve their verification goals faster.

On-Demand CadenceTECHTALK: In-Design EM Analysis Addresses RF System Integration Challenges

Join our one-hour CadenceTECHTALK to learn how challenges related to MMIC/RFIC integration can be identified and resolved prior to tapeout through in-design EM analysis and MMIC/RFIC co-simulation using distributed, multiprocessing EM analysis for large-scale RF structures with the Cadence’s Clarity 3D Solver and AWR Microwave Office circuit design software.

CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation

Register for a webinar that shows how Xcelium simulation enables design verification teams to catch low-power issues very early in the verification cycle at the RTL phase with best-in-class performance and providing complete low-power coverage.

2022 Cadence中国技术巡回研讨会—深圳站

2022 CadenceCONNECT: China Technology Day is coming soon! This year we will hold seminar in many cities including Shenzhen site. Cadence will bring you best practices and ideas. Come and join in us!

Training Webinar: Introduction to the Genus iSpatial Synthesis Flow

Genus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optimization. It provides excellent power, performance, and area (PPA) results in full flow. iSpatial technology enables front-end designers to make better design decisions faster by providing physical feedback about expected Place and Route (P&R) effects. This delivers better PPA results in complex SoC designs while maintaining quality and design schedules.

CadenceLIVE China 2022

CadenceLIVE China​ 2022 brings together Cadence technology users, developers, and industry experts to connect, share ideas and best practices, and inspire design creativity.​

ARMMS RF & Microwave Society Conference April 2023

Come and visit Cadence at our exhibition space from 17-18 April to discuss circuit, system, thermal, PCB and EM simulation for RF/microwave product development.

Training Webinar: Celsius Thermal Solver: Electrical and Thermal Co-Simulation

The Cadence Celsius Thermal Solver is the industry’s first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. The Celsius Thermal Solver seamlessly integrates with Cadence IC, package, and PCB implementation platforms, based on a production-proven, massively parallel architecture that delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

CadenceLIVE Silicon Valley 2023

CadenceLIVE Silicon Valley brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

Training Webinar: Enhance Layout Productivity with Virtuoso Concurrent Layout Editing

Join Cadence Training and Sr. Principal Education Application Engineer Baby Ravi for this free technical training webinar. We’ll cover topics offered in the Virtuoso Layout Pro: T8 Virtuoso Concurrent Layout Editing Course, guiding you towards concurrent layout editing for faster turnaround time, enhanced layout productivity, and quicker time-to-market.

CadenceCONNECT: CFD

CadenceCONNECT CFD will be held on April 19 at the Santa Clara Convention Center. The event will feature presentations from your industry colleagues that will offer solutions for today’s fluids analysis challenges that impact the design and development of tomorrow’s products.

CadenceCONNECT: Club Formal India

Cadence is pleased to once again bring you CadenceCONNECT: Club Formal, a platform for formal verification experts to come together and discuss the latest in formal technologies, including challenges, benefits, and best practices. Hear from your peers on how they are using formal verification techniques in their flows and interact with members of the Cadence® R&D team to discuss the technology, roadmap, and use cases. In this in-person seminar, you will hear an industry keynote, a Cadence R&D keynote on the latest in JasperTM technology, and several users who will discuss best practices. Plus, we will have deep technical demos and presentations by Cadence formal experts.

CadenceTECHTALK: Find Elusive Bugs Faster with Xcelium ML

Register for a CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles. This webinar will cover how Xcelium simulator with the Machine Learning (ML) App improves the efficiency of your regression environment, save CPU cycles, improves bug-hunting efficiency, and speeds up coverage closure.

On Demand: Addressing Instability in Wide Bandwidth High Power Amplifiers

Addressing stability in high-power amplifiers (HPAs) over wide bandwidths is one of the biggest challenges that RF PA designers must overcome. This webinar, presented by Dr. Dominic FitzPatrick, discusses the use of stability analysis in Cadence AWR Microwave Office software to identify the conditions leading to device instability and implement acceptable stabilizing solutions through circuit simulation in a 200W, wideband PA.

On-Demand CadenceTECHTALK: Tempus and DSTA

Cadence and Socionext invite you to an on-demand joint webinar. Register to learn how the latest innovations in the Cadence® Tempus™ Timing Solution can deliver faster time-to-signoff closure with the best power, performance, and area (PPA).

On Demand: Reappraisal of RFPA Modes

This webinar, presented by Dr. Steve Cripps, reviews recent work calling into question several well-established principles in RF power amplifier (PA) design. Conventional theory assumes that the active device current waveform is invariant with output voltage, but the “soft” IV knee characteristic of a gallium nitride (GaN) device, along with the inevitable presence of a second harmonic component in the output voltage waveform, cause some substantial changes to these conventional and widely-held results.

Training Webinar: Microwave Office—Comprehensive RF and Microwave Design Creation

Microwave Office is a comprehensive design environment for RF and microwave design creation. This webinar focuses on the electromagnetic simulation tools AXIEM and Clarity and their integration into Microwave Office. You can learn to simulate EM structures from the Microwave Office software’s user interface using the Clarity 3D Solver, a 3D full-wave EM simulation software tool.

On Demand: First Pass Design Methodology for a Broadband 100W RFPA

Learn about a broadband RF power amplifier (PA) design methodology for continuous wave operation using load pull for optimal impedance extraction, network synthesis, and electromagnetic (EM) analysis. The design uses a commercially available packaged gallium nitride (GaN) on SiC device and the integrated design flow within the Cadence AWR Design Environment platform to produce a first-pass reference design. Presented by Jack Brunning of SARAS Technology.

On Demand: Balun Design for a Wide Bandwidth L-Band 200W Power Amplifier

Review the application and design of a printed Balun suitable for L-band (1350-1850MHz) push-pull power amplifiers. The design begins with an idealized circuit simulation in Cadence AWR Microwave Office software using closed-form transmission line models followed by a more rigorous 2.5D planar EM simulation conducted using Cadence AXIEM 3D planar EM analysis. The webinar also covers measured results and techniques for analyzing the performance of components with non-50-ohm terminations. Presented by Dr. Dominic FitzPatrick.

ETHERNET & IP @ AUTOMOTIVE TECHNOLOGY DAY

Cadence is a Silver Sponsor at 2022 IEEE Ethernet and IP @ Automotive Technology Day. Cadence exhibits its Ethernet solution, which provides Automotive Ethernet MAC Design IP and Verification IP (VIP) supporting multiple speed grades from 10Mbps up to 10Gbps, including the latest Time-Sensitive Networking (TSN) standards, Ethernet rapid prototyping, and Cadence Sigrity technology for physical channel simulation. Cadence is also presenting a paper titled:“Layer 2 Security for Precision Time Protocol Frames for Automotive Ethernet”.

On-Demand CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges

The last webinar series, "Adopting a Faster, More Efficient Path to Multi-Chiplet Design," will address the growing system analysis challenges 3D-IC designers face related to signal, power, and thermal integrity and will demonstrate how facing these concerns through simulation during system planning and signoff accelerates the 3D-IC design cycle.

On-Demand CadenceTECHTALK: Mixed Signal SoC Verification Simplified with Xcelium Simulator

Watch this CadenceTECHTALK™ to learn how Cadence is providing effective verification and debug methodologies using RNM of analog blocks for mixed-signal SoC verification.

Technology on Tour: Club Verification Munich 2018 Proceedings

Download the proceedings from the Club Verification Munich event.

On-Demand CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

Next session in "Adopting a Faster, More Efficient Path to Multi-Chiplet Design" webinar series will help you to get a chip-centric perspective on performing PI and thermal integrity analysis in 3D-ICs from early planning to signoff.

On-Demand CadenceTECHTALK: Cadence Integrated Platform Solution for 3D-IC Design (Taiwan)

This webinar will discuss technology that proactively looks ahead through integrated early analysis, and addresses all aspects of 3D-IC design comprehensively, including system planning, packaging, implementation, analysis, and system-level signoff. It will discuss requirements and implementation flows for InFO, CoWoS, and SoIC, along with unique Pseudo-3D exploration capabilities that enable PPA push and the feasibility of 2D to 3D design conversion.

On-Demand CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

Join this next webinar in "Adopting a Faster, More Efficient Path to Multi-Chiplet Design" series to learn about the different approaches to 3D partitioning, implementation, and unique capabilities available with the Cadence® Integrity™ 3D-IC platform for bump planning, interposer routing, and top-down 3D partitioning and implementation.

CadenceLIVE Japan 2022

CadenceLIVE Japan 2022 will be held on July 15 at Yokohama Bay Hotel Tokyu. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

On-Demand CadenceTECHTALK: Helium Virtual and Hybrid Studio (Taiwan)

In this CadenceTECHTALK, we will show you the configuration and basic features of Cadence® Helium ™ Virtual and Hybrid Studio, a platform that accelerates the creation of virtual and hybrid prototypes of complex systems.

On-Demand CadenceTECHTALK: Efficient Multi-Chiplet Design with Cadence Integrity 3D-IC Unified Platform

Join the first session of a new CadenceTECHTALK series "Adopting a Faster, More Efficient Path to Multi-Chiplet Design" and learn about different packaging styles, innovative multi-technology database, integrated system planner, and an embedded analysis flow manager inside the Integrity 3D-IC platform, which provide a comprehensive, yet modular multi-chiplet design solution to help shorten the design cycle for all aspects of 3D-IC design and signoff.

Training Webinar: Getting the Most Out of Spectre

In this Cadence Training Webinar, we’ll focus on getting the most out of the Spectre Simulation Platform in terms of the performance/accuracy tradeoff. The goal is to maximize performance while preserving the trusted accuracy for which the Spectre Simulation Platform is renowned. We’ll guide you through each step of the process, from tool selection and initial configuration to troubleshooting convergence and debugging S-parameters.

On-Demand CadenceTECHTALK: What’s New in Clarity 2022.1

Watch the on-demand webinar on the Clarity 2022.1 release highlights, covering advances in meshing and frequency sweep technology, and revealing some significant advances that enable the secure integration of third-party mechanical components into your designs.

CadenceTECHTALK: 使用 Protium™ X2 加速复杂 SoC芯片原型验证

This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification.

Training Webinar: A Step Change in Custom IC Layout Productivity with Virtuoso Studio

This webinar highlights Cadence’s new productivity features and Virtuoso Studio’s improved performance for core layout. We’ll demonstrate in-design and in-memory signoff DRC and FILL with iPegasus Verification System for Virtuoso Studio as well as the seamless integration of the Innovus Implementation System. We’ll showcase how Virtuoso Studio helps to automate design migration across process nodes.

On-Demand CadenceTECHTALK: In-Design EM Analysis: Microwave/RF Design and Verification Workflows

Discover key best practices for proper electromagnetic (EM) analysis to help you achieve accurate simulation results in a short timeframe. This CadenceTECHTALK highlights CAD techniques for leveraging EM simulation to analyze and optimize designs much more rapidly than by using the sheer brute force of large numbers for distinct EM simulations.

On-Demand CadenceTECHTALK: Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator

Wondering how you can easily achieve up to 3X exemplary performance gains using Xcelium Logic Simulator. This webinar will provide a handy checklist of best practices covering umbrella performance switches, “access” levels, and simulation profiling to achieve the highest performance using Xcelium.

Training Webinar: Automating Bug Tracking with Verisium Debug and Python

The Verisium™ Debug Platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is a must. In this Training Webinar, you’ll learn how to automate your debug experience using the Verisium Debug platform with its built-in Python API.

2022 MATLAB & Simulink Smart Factory Forum -AI for Data Analytics

Join Cadence at 2022 MATLAB & Simulink Smart Factory Forum -AI for Data Analytics. Free registration to attend the virtual co-speech “System Design Challenges and Solutions for Smart Manufacturing” by Cadence Taiwan and Terasoft.

HPC芯片全流程验证解决方案专场研讨会 - 上海站

电子设计自动化领域领先的供应商 Cadence，诚邀您参加“ 2022 CadenceCONNECT: HPC芯片全流程验证解决方案”线下研讨会上海站。

On-Demand CadenceTECHTALK: Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows (Taiwan)

對下一代無線通訊、航太和運輸系統的需求正在推動對高性能、成本敏感的矽晶 RFIC 和 III-V 族化合物半導體單晶微波積體電路 (MMICs) 的需求，這些電路通常集成到先進的系統封裝 (SiP)中。 最新版本的 Cadence® AWR Design Environment® 平台讓產品開發團隊能夠透過Cadence Virtuoso® Design Platform 具備的廣泛射頻(RF) 到毫米波(mmWave) 設計、EM 分析和前後端工作流程的互通性，在更短周轉時間內滿足這些無線系統的高效能要求。 本場線上研討會將講述加速設計上手和平台設計共享的關鍵新功能，以提高工程生產力並確保一次性成功。

2023 Taiwan Telecommunication Annual Symposium

2023臺灣電信年會包含「全國電信研討會」、「橋接未來電磁研討會」與「消息理論及通訊春季研討會」，結合電信學門「電磁」、「通訊」、「訊號處理」及「網路」四個領域，研討會中將鎖定6G技術、毫米波應用、低軌通訊衛星、以及自主規格無人機等產業的技術開發議題，並邀請所有產業與學界專家期待有更進一步交流認識的機會。 Welcome to join Cadence speech at the 2023 Taiwan Telecommunication Annual Symposium about「EDA Innovation in Advanced Packaging」by Cadence expert. Cadence also has a two-day booth to introduce you more about Cadence and EDA industry.