Cadence custom simulation technology delivers all the tools required for designing and verifying your analog/mixed-signal blocks. The Spectre platform provides capabilities such as steady-state analysis for evaluating the noise and transfer functions of blocks, including dynamic comparators, time-to-digital converters, etc. Spectre X Simulator allows fast transistor-level simulations of large analog blocks (such as voltage-controller oscillators (VCOs)) while maintaining the accuracy expected of the Spectre simulation family. Spectre X Simulator redefines what an analog simulator can do.

This new feature of Optimization allows the design house to integrate their own optimization algorithm like machine learning into the standard Virtuoso flow. These algorithms are tailored to the technology using our extensive knowledge of circuit behavior. Embedded these algorithms, we could make optimization process more efficient to the direction we want.

A streamlined custom layout flow is introduced to speed up the layout implementation for analog circuit in an advanced process.  With this flow, a layout engineer can take designer’s design requirements from schematic to layout automatically and then do the layout floorplan and placement for the circuit based on those constraints to minimize any miscommunications on the requirements. Moreover, a new ART (Advanced Routing Technology) router is also adopted to realize the connectivity of devices by using a user-defined pattern track called WSP (Width Spacing Pattern).  By using this new custom layout flow, we can automate some layout procedure and  then improve layout productivity for analog circuit compared to the traditional fully manual layout flow.

The mass application of MIPI D-PHY and C-PHY has resulted in fast and diversified development. Over the past decade, we keep commercial-wise devices like smartphones and IoT stay-tuned, while the automotive field has been growing immensely. Although the safety concern and design robustness are much more rigorous, the progressive EDA tool support and circuit design make it feasible.  In advanced technology, plenty of design issues need to be solved, such as timing closure, physical effects, IR-drop analysis, and reliability. These issues are taken into account when using the Cadence Innovus Implementation System, Voltus IC Power Integrity Solution, and ADE. In this presentation, the safety and reliability concern of automotive-related product is discussed in advance. Then, an example of MIPI C/D-PHY combo design is demonstrated. The cooperation status and summary are mentioned lastly.

Kneron Company Overview  Next Generation AI SOC in Kneron  Tensilica DSP Application in Kneron

As chiplets and advanced packaging go mainstream for AI, HPC, networking, and more other applications, IP and EDA support with silicon-proven and correlation are crucial to the success of the ASIC. It requires close collaboration among foundry, tool and IP vendors, and ASIC service providers to overcome new challenges and ensure product success. GUC and Cadence’s collaboration on HBM3 and 112G SerDes CoWoS platform demonstrates a good example of cooperation.

LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI and networking. Cadence LPDDR5X IP is designed to enable the industry’s next-generation SoC designs for these and other applications with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.

Advanced process nodes and chiplet-based designs are pursuing increased capability with improvements in power, performance, and area.  This is driving the need for enhanced visibility within devices for many effects: design sensitivities, material variability, latent defects, accelerated silicon aging, and the impact of software on hardware. New methods are needed to ensure the design meets usage requirements. From characterization and qualification, through test, and during lifetime operation in the field, a predictive approach is needed. This presentation will highlight a new approach by proteanTecs for health and performance monitoring of advanced electronics from design to the field, using deep data analytics. By combining on-chip agents (monitoring IPs) with ML-driven analytics, manufacturers and service providers can roll out devices with mega-functionality, at scale - safely, reliably and cost effectively. By fusing measurements from the agents, design simulations, and customer data, the company provides newfound insights for mission-critical applications, such as datacenter, mobile and automotive.  We will review the Cadence implementation workflow for integrating proteanTecs technology, in use today at leading semiconductor companies.  Leveraging the capabilities of Innovus and Spectre, we have simplified the implementation process and improved device learning.  As a provider of both soft and hard IPs that are inserted into an existing functional design, proteanTecs minimizes the effort by the user through the use of Cadence tools.

As autonomous vehicles and driver assistance systems increase in demand, how can we efficiently design and verify automotive ICs?  In this presentation, we will introduce 3 ways MATLAB/ Simulink integrate with Cadence tools and share 2 types of verification methods to verify an automotive radar sensor. 1. Virtual Field Trials: build driving scenarios using the Driving Scenario Designer app in Automated Driving Toolbox. 2. Early Verification of Datasheet-Level Metrics: Reduce repetitive model development through integrating MATLAB/Simulink into Cadence SV/UVM-based verification environments.

By Reinforcement Learning ML driven optimization, Cerebrus creates automated design flows for PPA improvements. However after investing many time and machines, some results were not enhanced.  We found that even the smart ML based Cerebrus, it needs a good-enough base input data,  such as a floorplan with controlled overflow, clean SDC files, correct clock skew group setting. In this paper/talk, we discuss how to co-work with Cerebrus to enhance our 5G modem CPU PPA. And what might be the pitfalls  and how to avoid it.

GUC shares Cerebrus experience in variety of designs, showing Cerebrus can achieve good PPA and shorten the overall project implementation iterations.

Speed determines the winner. Nowadays, there is a trend in advanced IC design shows published product with tight schedule and high-performance spec. Over the past two years, Mediatek has continuously upgraded the spec of their flagship chip series, Dimensity. For an example, comparing the spec with Mediatek Dimensity 1000 in 7 nm process, the latest Dimensity 9200 uses 4 nm process, and has increases 52% CPU performances, 41% GPU performance, and upgraded the resolution to 8K, etc. In overall, Mediatek Dimensity 9200 concludes over 17 billion transistors. Designs with more transistors often have higher structural complexity, which could make the adjustments in design quality more challenging to achieve its spec. Conventionally, designers adopt synthesis to evaluate design quality. However, an increase in design complexity would also raise synthesis runtime. Additionally, if the design quality does not meet spec, iterations are necessary to tackle design bottlenecks, the iterations consume schedule and human resources. Therefore, it is important to improve efficiency in enhancing design quality to meet   spec within schedule constraints. In this presentation, we will introduce how to use Cadence Joules RTL Design Studio to improve the efficiency on design quality enhancement. Joules RTL Design Studio is an EDA tool enabling rapid design evaluation and bottleneck diagnosis. In our experiment, Joules RTL Design Studio reduces 50% run-time for evaluating design quality in a single run against to Cadence Genus with merely 5-10% performance gap. In addition, Joules RTL Design Studio could diagnose and point out the design bottleneck for designers so that the manual analysis effort could be significantly reduced.

With the advancement of the manufacturing process, designs are becoming more complex, leading to increased considerations for EDA tools. This results in longer runtime requirements. These challenges have significantly impacted engineers' work efficiency and debugging fault tolerance. As the most crucial architecture in mobile chipsets, the CPU has particularly high demands for runtime efficiency. Otherwise, project progress and quality could be greatly affected.  In collaboration with Cadence, MediaTek CPU team successfully uses smart hierarchical flowe, which has been verified to improve overall TAT Reduction significantly.

As the design process continues to shrink, the SoC design within Novatek reaches over millions of instances. In this work, we offer two results of our investigation into Voltus. First, even though Voltus has significantly boosted its performance by using distributed processing technology (XP) for power grid analysis, it takes over one day per iteration to complete a flattened IR-drop analysis. Initially, Voltus-XP was restricted solely by the distributed analysis over the chip power rail.  Nowadays, Voltus-XP is also available for distributed analysis over chip power calculation. In this work, we combine these two distributed power calculation and rail analysis solutions for an additional improvement in operating time. In addition, Voltus-XM is an alternative solution for hierarchical IR closure. Just as the timing analysis tool adopts the timing model upon partition timing closure or drastically reduces the turn-around time upon flattening timing closure. Voltus-XM is able to generate a xPGV model that represents the current and partial power mesh of each partition. With the adoption of xPGV, reduced turn-around time and hierarchical IR closure would be realistic. To efficiently and correctly solve IR-drop in a partition, we also present our correlation result by the deviation of xPGV and flatten IR to demonstrate its effectiveness.

IEEE1801 power states can be configured through several power state tables and could be at different scopes crossing several files. It's difficult (almost impossible) to derive the supply relationship manually by cross-checking all the power state tables. Resolving the power state issues such as conflict states is important since the design low power analysis is performed based on global consistent power states. This feature identifies the power intent and power state checks without requiring designs. This support provides a fast turnaround time for power state table checks and flexible usage to allow users to configure the used checkers.

Over the years, Cadence has developed significant processes for advancing multiphysics system analysis. There are multiple innovative products coming to this field, including Cadence's Clarity, Celsius, Sigrity X, Optimality, and Fidelity solutions, that deliver remarkably greater performance than existing technologies in the market. To provide a comprehensive multiphysics system analysis product portfolio, we acquired the best-in-class simulation technologies from Integrand, Pointwise, Cascade, and Future Facilities, spanning the multi-dimensional domains that cover signal and power integrity (SI/PI), electromagnetics, thermal management, and computational fluid dynamics (CFD). As we continuously innovate and excel in this fast-growing field, our team provides revolutionary technologies to accelerate the simulation process for our users and customers.  Focusing on generative AI technology, last year we announced Optimality Intelligent System Explorer, the industry's first AI-driven system design optimization solution, which has been highly integrated with our proven Clarity and Celsius technologies to reduce design respins that help our customers achieve magnificent productivity gains. Already providing tremendous design optimization benefits for our customers, the Optimality technology is now in the process of integrating with Cadence's Allegro design platform to further revolutionize the workflow for PCB and IC package designs.  We are dedicated to adopting heterogeneous hardware technologies to accelerate simulations by porting our simulation products to different CPU/GPU platforms and are excited to bring significant advancements to optimize design productivity.

In designing high-speed signals on PKG and PCB, especially with a complex system architecture, it is powerful to find out optimized design automatically rather than engineers do trial and error manually. This talk focuses on the importance and development of automatic optimization for high-speed interface based on Cadence Optimality. A generic flow and design concepts for the frequency response of a high-speed channel will be introduced first. Then, an example package layout demonstrates the feasibility of the proposed optimization algorithm with defined cost function. With Cadence Optimality, the return loss (RL) and far-end crosstalk (FEXT) could be improved by a good amount, respectively. Finally, the benefits of using optimization algorithms to sign-off SI/PI performance in the future will be discussed.

Material characterization is a critical step in PCB ecosystem enabling. Delta-L methodology is good in the electrical characterization with the de-embedding to remove the unwanted effect, such as the via.   In this presentation, Delta-L coupon design and test concept will be introduced. The novel serpentine trace design is designed by Clarity 3D and Optimality to enhance the PCB panel utilization with lower PCB cost.

We have established a collaboration with Cadence, a leading EDA tool provider in the industry, who has introduced an innovative tool known as Clarity. Clarity is a 3D FEM (Finite Element Method) simulation tool that incorporates advanced mesh technology. During this presentation, we will not only present a comprehensive comparison with other third-party tools, utilizing multiple case studies but also delve into our valuable experiences in enhancing the efficiency of our simulations.  By sharing these insights, we will demonstrate Clarity's remarkable capabilities and benefits in our simulation processes.

With the advent of mobile processors integrating CPU and GPU, high-performance tasks, such as deep learning, gaming, and image processing, are running on mobile devices. To fully exploit CPU and GPU's capability on mobile devices, we need to utilize their processing capability as much as possible. However, it is challenging due to the nature of mobile devices, whose users are sensitive to battery consumption and device temperature. Thermal management is essential to the temperature and power consumption below predefined thresholds to enable energy-efficient operations in mobile processors.  In this presentation, an innovative methodology has been developed for real-time thermal management. The method provides a fast thermal RC circuit solver for real-time thermal feedback and a Python API module to incorporate with the device power control system. Its accuracy and performance have been validated with finite element solution and silicon measurements.

This presentation introduces some methodologies to increase performance of simulation and debug with Xcelium and Verisium as MSIE, MCE and VWDB etc. That session will also share experiences of CPF to UPF. Using VCT and some option to get accurate information to avoid wrong low power simulation.

Introduction the method to build virtual driver on Palladium and to emulate the full virtual system. And using Cadence’s GSFIFO input stream to speed up the virtual device communication.

To successfully tape out the the SoC of AI-application or High-performance computing with huge design complexity and verification scope, plan ahead for verification flow, resource assessment, and resource allocation is fatal for successful tape out. Would like to share what we need to get prepared for conquer these verification challenges during project execution

With the functional requirements, means of conducting function verification and performance emulation have become increasingly complex. In addition to requiring high partition effort, prototyping platforms such as Protium possess physical interface limitations. Alternatively, utilizing pure RTL simulation may consume a significant amount of time. These solutions are inadequate in testing corner cases and emulate performance. We aim to leverage Palladium to address these limitations. With its unlimited capacity and a rich variety of speed bridges for every kind of physical interface, functional coverage and performance emulation can be successfully verified and evaluated.  Thanks to this robust platform, DE, DV, and SW teams can collaborate effectively. In addition to enhancing debugging efficiency, Palladium brings us closer to achieving real chip emulation.