CadenceLIVE India – OnDemand
Advanced Verification Methodology
UVM-Based Generic Interrupt Handler
Debarati Banerjee, Google
Nikhil Singla, Google
Shantha B, Google
Shan Velusamy, Google
AVM-02
Bottoms-up Approach to an Accelerate SoC CDC Setup and Analysis
Gift Babu Yeluri, Texas Instruments
AVM-03
Accelerating Functional Safety Verification and Optimization of Fault Lists in the Scope of ISO26262
Risita Jena, Texas Instruments
Anant Sharma, Texas Instruments
Ashwini Padoor, Texas Instruments
Arun Shrimali, Texas Instruments
Jasbir Singh, Texas Instruments
Vinay Rawat, Cadence
AVM-04
Target Diagnostic Coverage is Achieved! What about Unclassified Faults?
Siri Rajanedi, Analog Devices
Prashantkumar Ravindra, Analog Devices
Sheetal Swaroop Burada, Cadence
Sriniwas Narayan Murthy Budi, Cadence
Vinay Rawat, Cadence
AVM-05
Shift Left Methodology for Verification of Isolation Strategy in Low-Power Design using LPS Query
Ayush Agrawal, Samsung
Atiq Jamadar, Samsung
Subramanian R, Samsung
Sekhar Dangudubiyyam, Samsung
AVM-06
Xcelium-ML: The Way Forward for Better and Faster DV Closure
Parthasarathy Ramesh, Texas Instruments
Rajat Mehrotra, Texas Instruments
Harish Maruthiyodan, Texas Instruments
Aanchal Sachdeva, Cadence
John Rose, Cadence
Prashanth A, Cadence
AVM-08
Boosting Complex Serial Interfaces Debug Productivity using Waveform Debugger
Sai Nikhil Kandukuri, Associate Staff Engineer
Ajay Kumar Gunji, Samsung
Bhargavram Hegde, Samsung
Swathi B N, Samsung
Garima Srivastava, Samsung
Sunil Shrirangrao Kashide, Samsung
AVM-09
Comptational Fluid Dynamics
Numerical Investigation of a Ported Shroud Effect on the Performance of a Supercritical CO2 Compressor
Ramanakanthan Rajkumar, Triveni Turbines
Gaurav Giri, Triveni Turbines
Hayagreeva Rao, Triveni Turbines
CFD-01
Optimum Design and Analysis of Ram Air Cooled Systems of a 19-Seater Turboprop Aircraft
Niranjan CK, NAL
CFD-02
Use of 6SigmaRoom for Design of a Large Data Centre
Dr. Munirajulu M, L&T Constructions
Sushil Surwase, L&T Constructions
Balakrishnan R, L&T Constructions
CFD-03
A Numerical Study for Self-Propelled Bulk Carrier With and Without Energy Saving Device Using Actuat
Venugopal J, SEDS India
Rahul Sharma, SEDS India
Sachin M, SEDS India
Vivek Ramanath, SEDS India
CFD-04
Comparative Analysis of Experimental and Computational Compressor Maps for a Centrifugal Compressor
Kishore Kumar C, Gas Turbine Research Establishment
Kirubakaran P, Gas Turbine Research Establishment
Prithivirajan G, Gas Turbine Research Establishment
Jaiprakash Anand, Indian Institute of Science
CFD-05
An Overview on Thermal Management of the Electronic by Using Celsius EC Tools
Naveen G Patil, Varroc
CFD-06
Efficient Thermal Management for Enhanced Electronics Performance
Jeevan Kumar B, Cadence
CFD-07
Custom and Analog Design: Implementation
Custom Automatic Dataset (CAD) Generation Flow for EAD and SDR
Sathish Rao, Marvell
Dhanesh Kumar Pragasam, Marvell
Sandeep Torgal, Marvell
CADI-01
Improved Productivity and Quality of Layout Designs with Virtuoso Studio
Deep Shikha, STMicroelectronics
Akshita Bansal, Cadence
Devendra Gupta, STMicroelectronics
Vishesh Kumar, Cadence
Prachi Solanki, STMicroelectronics
Rajeev Singh, STMicroelectronics
CADI-02
Schematic Design-Driven Automated Layout Methodology using Virtuoso Auto-Place and Route
Manjari Agrawal, NXP Semiconductors
Manish Kumar Upadhyay, NXP Semiconductors
Urvashi Jindal, NXP Semiconductors
Akshita Bansal, Cadence
Vishesh Kumar, Cadence
CADI-05
Symmetric and Interactive Signoff Metal Fill for Parasitic Sensitive Analog IPs in Virtuoso Studio
Atul Bhargava, STMicroelectronics
Monika Lilani, STMicroelectronics
Sahab Abdul Hadi, Cadence
Efim Shumilov, Cadence
Vishesh Kumar, Cadence
CADI-06
Power Mesh Tool
Kuldeep Tayade, Alphawave Semi
CADI-08
Custom and Analog Design: Verification
A Ray of Hope for Full-Chip AMS Simulation – Advent of Spectre FX Fast-Spice Simulator
Vijay Kumar, Samsung
Sushma Pattanashetti, Samsung
Anand Subramanian, Samsung
CADV-01
Advanced Safe Operating Area Checks Based on 10-year DC Foundry Data using Spectre Assertions
Mayank Chakraverty, ams OSRAM AG
CADV-02
Characterization of a Radar Transceiver Utilizing the Liberate AMS Tool
Vasant B, Steradian Semiconductors
Amit Kumar Kabat, Steradian Semiconductors
Siddalingesh Walishetra, Steradian Semiconductors
Vineeth Anavangot, Steradian Semiconductors
Rajni Dhiman, Cadence
Helen Shi, Cadence
CADV-03
Enabling Smartview-Based Efficient Post-Layout Simulation and Advanced EM-IR Analysis
Subhrajyoti Saha, Texas Instruments
Sonu Gill, Texas Instruments
Shrinidhi Muddebihal, Texas Instruments
Girish Bijjal, Texas Instruments
Subhadeep Ghosh, Texas Instruments
Ajoy Mandal, Texas Instruments
CADV-04
High-Speed ΔΣADC Design with Full Cadence Custom Flow for Accurate Results with 2X Performance Gain
Vaibhav Garg, STMicroelectronics
Prayes Jain, Cadence
CADV-05
Overcoming the Challenges and Complexities in eFuse IP Characterization using Liberate MX
Srujana Pillay, GlobalFoundries
Nilangshu Das, Cadence Design Systems
CADV-06
Seamless and Efficient Power Integrity Signoff Flow using Voltus-XFI
Elangovan N, Marvell
Prabhakar Karpotula, Marvell
Bhanuprakash Raghavapuram, Cadence
CADV-07
Liberate MX Trio to Enable Memory Characterization for Complex and Third-Party Memory IPs in STMicro
Shreyash Tripathi, STMicroelectronics
Jean-Arnaud Francois, STMicroelectronics
Sachin Gulyani, STMicroelectronics
Gudapati Sai Krishna, Cadence
Swathi M N, Cadence
Dhanush J, Cadence
CADV-08
Unified Analog Mixed-Signal Defect Simulation and Applications
Aswin R, Texas Instruments
Chanakya K V, Texas Instruments
Arshad Qureshi, Texas Instruments
Supraja R, Texas Instruments
Lakshmanan Balasubramanian, Texas Instruments (India) Pvt. Ltd.
Vinay Rawat
CADV-09
Digital Design Advancement with AI
Area and Performance Improvement With ML-Based Opt Engine: Cadence Cerebrus – A Case Study
Aswin P, Texas Instruments
Sanjana Sundaresh, Texas Instruments
Vishwa Prabhat, Cadence
Bala Posina, Texas Instruments
Sunil Mederametla, Cadence
Suman Prasad, Cadence
AI-01
Power Optimization on High-Performance Designs using Cadence Cerebrus ML Flow
Rahul Mandal, Marvell
Balamurugan Sekar, Marvell
Kiran Kumar, Marvell
Anup Kumar, Cadence
Sharath A C, Cadence
AI-02
Digital Design and Implementation
Achieving Optimized PPA for SiFive’s P670 Processor using Cadence Digital Flow on Samsung SF4X
Shamanth Kolli, SiFive
Rashed Islam, SiFive
Yawar Abbas, Cadence
DDI-01
Big DIE - High-Performance Computing Design Convergence in Cutting Edge Technology
Ravi Shankar Reddy Kanala, Samsung
Suresh G, Samsung
Karthik Arlithaya, Cadence
Saidi Reddy A, Samsung
Vishal Kumar G, Samsung
DDI-03
Concurrent Macro Placement (CMP) and Flash PG (Power Grid) usage in Innovus
Siva Anala, GlobalFoundries
Nitish Kumar, GlobalFoundries
DDI-04
DCLS Implementation and Verification with USF for Automotive Chips
Deepika Madaan, STMicroelectronics
Harshal Sureshrao Ambatkar, Cadence
DDI-05
Physical Implementation of Functional Safety (FuSa) Features in Automotive Chips
Shashikiran Srinivasa, Marvell
Anup Kumar, Cadence
Rahul Mandal, Marvell
DDI-07
Runtime Reduction using Flash PG
Siddharth Kanakamedala, Broadcom
Tejas Bhalla, Broadcom
Amarnath N, Cadence
DDI-08
Advanced Dynamic Power Optimization Techniques Driven by Joules Xreplay
Aditya R, Arm
Naga Yashas S, Arm
DDI-09
Digital Front-End Design and Test
Comprehensive Low-Power ATPG for Complex Low-Power Designs using LPG Technology
Nitesh Mishra, Texas Instruments
Rupesh Lad, Texas Instruments
Aalin Sabatni, Texas Instruments
Vinay Chowkimath, Texas Instruments
Ninad Khire, Texas Instruments
DFD-02
Hierarchical Test Flow - An Effective Way of DFT Implementation
Bhavik Parikh, einfochips
Mayurrajsinh Jadeja, einfochips
DFD-03
Reducing Test Data Overhead and Test Power using Cadence Modus DFT Software Solution
Pranjal Giri, Texas Instruments
Prateek Giri, Texas Instruments
Mudasir Kawoosa, Texas Instruments
Pervez Garg, Texas Instruments
DFD-04
Using Stratus HLS to Quickly Optimize the Area of a Module used in a Single Chain WLAN Receiver
Sheetal Jain, Infineon Technologies
DFD-05
Techniques for Efficient and Accurate Power Estimation
Chirag Sharma, Texas Instruments
Anuvrat Srivastava, Texas Instruments
DFD-06
Complex Design Scenario Exposing Corner Case ATPG Tool Issues at Handling At-Speed Timing Exceptions
Ravi Kiran, Analog Devices
Thirukumaran Natrayan, Analog Devices
Shiva Patil, Analog Devices
DFD-08
Physical Aware TPI and Scan Wrapper Insertion to Optimize Gate Count and Routing
Abhishek Mahajan, NXP Semiconductors
Navdeep Sood, Cadence
Ankur Gupta, Cadence
Sakshi Goyal, NXP Semiconductor
DFD-09
Digital Signoff
Fast and Accurate Hierarchical Timing Analysis using Tempus SmartScope Solution
Jishnu Mukherjee, NVIDIA Graphics
Ulhas Kotha, NVIDIA Graphics
Benny Ulf Goran Widen, NVIDIA Graphics
Daksh Bakshi, Cadence
Niharika Gupta, Cadence
DS-01
In-Design Optimization for IR and Yield Improvement using Pegasus Based MIMCAP and LPA Integration
Anuradha Shankar, Samsung
Anil Kumar Kasula, Samsung
Pratapsinh Ghule, Samsung
DS-02
Liberate Solutions for Next-Generation Standard Cell Characterization Needs
Nitin Bisht, Texas Instruments
Shimoli Rajendra Shinde, Texas Instruments
Prashanth Kumar A, Texas Instruments
Varun Ithal, Texas Instruments
Gaurav Varshney, Texas Instruments
Ajoy Mandal, Texas Instruments
DS-03
Nipping "Signoff" DRCs Through Budding "Pegasus" Solution
Rashmi Raut, Arm
Abhijit Pradeep, Arm
DS-04
Voltus-XP Readiness for TI Designs
Rishabh Singh, Texas Instruments
Ananya Pal, Texas Instruments
Subhadeep Ghosh, Texas Instruments
Ruchin Gupta, Cadence
Sushant Sharma, Cadence
Ajad Kumar Kushwaha, Cadence
DS-05
Hierarchical Design Optimization Using Certus ECO Solution
Anil Kumar Kasula, Samsung
Tony Mathew, Samsung
Manish Tikyani, Cadence
Praveen Kumar Gontla, Cadence
DS-06
Challenges and Solutions to Achieving Overnight Signoff
Abhishek Tripathi, Arm
Avinash Tagore Salla, Arm
DS-07
Timing Robustness: Tempus-PI - A Way Forward for Analyzing Timing-Voltage Sensitive Paths
Shourya Shukla, Marvell
Lavanya Padmanabhuni, Marvell
Harshit Jaiswal, Cadence
Sharath A C, Cadence
Nitin Jain, Cadence
DS-08
Hardware and System Verification
A Novel Framework to Accelerate System Validation on Emulation
Manoj Sharma Khandelwal, Samsung
Rinkesh Yadav, Samsung
Sarang Kalbande, Samsung
Garima Srivastava, Samsung
Hyundon Kim, Samsung
HSV-01
Securing Design Quality for Low-Power Feature of Imaging SOC - Reuse of UVM sim tb on Acceleration
Vivek Kumar, Samsung
Manish Mallan, Samsung
Karthik Majeti, Samsung
Gurvinder Singh, Cadence
Kanishka S, Samsung
HSV-02
Tackling the Verification Complexities of a Processor Subsystem using Portable Stimulus
Vivek Gopalkrishna, Analog Devices
Ponnambalam Lakshmanan, Analog Devices
Sandeep Katti, Cadence
Ranjith Sankaranarayanan, Cadence
HSV-04
Protium: The Key to Accelerate System Development
Nivedita Nair, Analog Devices
Ajeet Mall, Analog Devices
Ashok Chandran, Analog Devices
HSV-07
Complex Interconnect Verification and Performance Analysis using System VIP on Multi-Die 3D-IC Systems
Saravanakumar S, Samsung
Sarita Sharma, Samsung
Jyoti Verma, Samsung
Sekhar Dangudubiyyam, Samsung
Avit Gururaj Kori, Cadence
Gnaneshwara Tatuskar, Cadence
HSV-08
Complex Interconnect Verification and System Performance Analysis at SoC using System VIP
Ravin Shah, STMicroelectronics
Sumit Singhal, STMicroelectronics
Jagtar Singh, STMicroelectronics
Manasi Hate, Cadence
HSV-09
PCB & System Design and Analysis
Automotive GMSL2 and FPD Link3 Simulation using Clarity 3D
Madapana Lokeswar, Valeo
Sneha Sridhar, Valeo
PCB-01
Allegro PCB Design True DFM Technology
Jayasimha BR, Sienna ECAD Technologies
Guruprasad Mk, Sienna ECAD Technologies
Savitha R Ganjigatti, Sienna ECAD Technologies
PCB-02
Allegro System Capture Redefining Design
Raghavendra Anjanappa, Micron
Amithkumar Dani, Micron
PCB-03
Debugging Automated Test Equipment Boards Through InspectAR Augmented Reality Tool
Sanoop Sukumaran, Texas Instruments
Srinivasan S, Texas Instruments
PCB-04
High-Speed System-Level Simulation using CAT 6 Ethernet Cables
K. Vijaya Varma, L&T Technology Services
NM Siva Kumar, L&T Technology Services
K Vijaya Varma, L&T Technology Services
Panchakshari Sr, L&T Technology Services
PCB-06
Impact of Via Stub on Signal Quality of a Parallel Interface
Anusha Karumuri, Western Digital
Ajay Dhingra, Western Digital
PCB-07
Integrated System Design Using the Allegro X Design Platform for Next-Gen Power Electronics-Based Products
Bala A, Syrma SGS Technology
Vikramjit Singh, Syrma SGS Technology
Aravinth D, Syrma SGS Technology
Karthikeyan M, Syrma SGS Technology
PCB-08
RLC Extraction using Sigrity for the Best Layout Optimization
Santhosh Rangasamy, Infineon Technologies
Desai Ronak, Infineon Technologies
Purshothama Rao, Infineon Technologies
Santoshkumar Gurral
PCB-09
Performance and Smart Bug Hunting
Exploring Verisium to Expedite IP Simulation Debugs Originating from Incremental RTL Updates
Janaakiram Jajji, Samsung
Sabari Ghosh, Samsung
Het Shah, Samsung
Ratan Deep, Samsung
Harsh Setia, Samsung
Bitu Kumar, Cadence
PSBH-01
Accelerating Datapath Verification using Formal Techniques
Bhavya Dasari, Texas Instruments
Jaaneshwaran Arulmozhi, Texas Instruments
Karthik Rajakumar, Texas Instruments
Vivek Raheja, Cadence
Craig Deaton, Cadence
PSBH-02
Addressing Design Verification Challenges for Security Subsystems and Cryptographic IPs using Formal
Arjun Suresh Kumar, Samsung
Kedar Swami, Samsung
Ravi Teja Gopagiri, Samsung
Anil Deshpande, Samsung
Somasunder Kattepura Sreenath, Samsung
PSBH-03
Scaled-Up Design Signoff using Formal Verification
Anushka Dixit, NXP Semiconductors
Gaurav Jain, NXP Semiconductors
Mohit Kumar, NXP Semiconductors
Anshul Singhal, Cadence
PSBH-05
A Case Study on the Verification of Latest PCIe Gen6-PHY using Cadence PCIe VIP
Kanak Rajput, Samsung
Sarath Yadav Saginala, Samsung
Deep Mehta, Cadence
Vishnu Prasad K V, Cadence Design Systems
Parag S Lonkar, Samsung
Nitin Yadav, Samsung
PSBH-06
Accelerating PCIe 4.0 Switch Design Verification: Compliance Testing using Cadence Triple Check Sol
Murugan Ambigabathi, MediaTek
Ginu Varghese, MediaTek
Deep Mehta, Cadence
Ezra K, Cadence
PSBH-07
FPV: How to Find Bugs Before They Find You
Arushi Mittal, Google
Rohit Bansal, Google
PSBH-08
Accelerating GLS Simulation Closure Using Hybrid GLS Methodology
Kumar Teja Kalava, Digital Design Engineer
Ashwini Padoor, Texas Instruments
Pankaj Talwar, Texas Instrument
Venkatesh Lingaiah, Cadence
Kavithaa Rajagopalan, Texas Instruments
Desmond Fernandes, Texas Instruments
PSBH-09