CadenceLIVE Europe – OnDemand

In this presentation a System-on-Chip (SoC) for AI algorithms will be presented which was designed by Dream Chip Technologies and is produced in 22nm technology (GlobalFoundries22FDX). The development concept includes the design and layout of a SoC with hardware acceleration for AI and a safety concept for critical automotive applications, and the software development of a tooling and compilation environment. With 1.8 billion transistors, the SoC is one of the most complex digital chips ever funded by the BMBF and achieves an overall performance of 10 TOPS for AI algorithms. The core elements of the SoC are the energy-efficient hardware AI accelerators for use in safety relevant applications in automotive and industrial sectors. In addition, a 20 MPixel real-time image signal processor (ISP) with ASIL-B/-D and ISO26262 certification for the automotive market is integrated. This ISP core from Dream Chip Technologies can support 16 cameras. The SoC enables fully quantized neural networks and flexible bit widths per layer, without the need for any floating-point operations for precision preservation. A RISC-V core enables flexible memory schedules to tile and fuse different neural network workloads. An Apache TVM-based compilation flow is in development to find the optimal workload mapping on the hardware. The aim of the project is to build the first step of the Dream Chip Technologies AI SoC roadmap. It will be continued with commercial SoC tape-outs in 2024.In addition to the technical development goals, the aim is to gather development partners around Dream Chip Technologies to simplify and broaden the use of AI solutions.

This paper presents the optimizations performed in X-FAB digital IP in terms of design and test recommendations focusing on Cell-Aware Test methodology using Cadence flow. The safety related applications such as automotive and medical applications have more and more stringent quality requirements. To achieve this quality level, digital designers have to take care about: - defect occurrence reduction: this paper will describe how the X-FAB digital IPs reach the right tradeoff between Design for Manufacturing (DfM) robustness and Best-PPA (power performance area) achievement - defect detectability increase: for that, this paper is focusing on the test methodology named ATPG Cell Aware Test (CAT) which theoretically increases the test coverage compared to ATPG covering classical stuck-at, transition or bridges faults because the CAT takes into account the cell internal transistors to generate scan patterns while the classical ATPG patterns are generated by considering the standard cells as black-box and only based on truth table of the standard cells. This paper will describe the outcome of analysis of this CAT benefit on experimental test chips where defects have been intentionally introduced by design on location identified as undetectable by fault simulation tool as Legato Reliability Solution.

Modern vehicles are equipped with several cameras, which provide a vast amount of real-time information about the environment as well as of the interior of the vehicle. The information in the captured images can be extracted by state-of-the-art deep neural networks with high accuracy. Since these algorithms require a huge amount of processing power and energy, sophisticated HW is needed to run them in real-time. In our work, we focus on developing a mono camera-based system, which captures images from the side mirror perspective with integrated 3D object detection and tracking run on the Cadence Tensilica NNA110. Such a system improves safety in different situations and enables for ADAS applications, like a turning assistant, which alerts the driver when pedestrians or cyclists are about to cross the vehicles path, a door opener warning in case a cyclist is approaching from the back, or a lane change assistant. From each RGB image 3D boxes, described by their positions, dimensions, and headings, are extracted for four classes of objects (pedestrians, bicycles, vehicles, motorcycles). The object detector is based on the CenterNet architecture combined with an EfficientNetV2 as the backbone, providing a good balance between efficiency and accuracy. The detected objects are furthermore tracked over time by applying a matching and several temporal filters. This enables to extract more detailed information on the objects, like trajectory extraction, object velocity, and path prediction. The presentation will highlight the following aspects: the intended application, architecture of the CNN for 3D object detection, training and training data set generation, results of accuracy analyses, the implementation on the Cadence Tensilica NNA110 including toolchain and performance values based on simulation results, as well as the latest automotive SoC developed by Dream Chip Technologies in 22FDX, which features the Cadence Tensilica NNA110 and Dream Chip Technologies’ automotive 20 MP dual RPP image signal processor. It targets the application described above by supporting up to 16 cameras and includes additionally a dual ARM A65AE with 1.2GHz, DCLS ARM R52, PCIe G3, MIPI Rx and Tx. The total AI processing performance is 10 TOPS (INT8). The NNA110 is running at max. 950 MHz and features 3.8 TOPS. HW key figures are presented, such as area, energy consumption, and clock frequency. Finally, the implementation is compared to those on other state-of-the-art architectures.

Modern SoC designs are getting more and more complex and the according software involved is becoming a more and more significant part of the product. This also increases the need to start software development as soon as possible. It should ideally begin right after the system architectural design is finished and before any hardware is developed and manufactured. Besides an appropriate toolchain and a development environment the system platform itself is a fundamental base for efficient software development to verify, test and run the software. Consequently, there is an urgent need for the software developers to have an appropriate platform. Nowadays, SoC CPUs can efficiently be emulated by software on a host computer. Additionally, SystemC TLM2 software models of custom or 3rd-party modules are widely available and can be used to form a virtual platform that almost exactly represents the final SoC design on transaction level. At this point the Virtual Prototyping platform enters the game. The Cadence solution Helium Virtual and Hybrid Studio offers a complete environment to design an appropriate Virtual Platform. The intuitive GUI based environment is designed to easily add and connect existing SystemC TLM2 models and removes the burden to set up a platform by replacing handwritten boilerplate SystemC code with automatic generated infrastructural connections under the hood. Furthermore, it provides debug capabilities for the embedded source code as well as debug options for the SystemC models code itself by providing features like register observation, and internal transaction tracing and profiling. The possibilities of Helium Virtual and Hybrid Studio to speed up software development has been evaluated in the context of the Zuse KI-mobile project. For this purpose, a simplified heterogeneous multi CPU SoC platform was designed with existing SystemC TLM2 models. Debug and profiling options to the corresponding involved embedded operating systems has been tested and assessed. We will summarize and present the results of this evaluation.

LiDAR (Light Detection and Ranging) technology has emerged as a key enabler for advanced driver assistance systems (ADAS) in the automotive industry. This presentation focuses on the motivation behind the adoption of LiDAR in the automotive driver assistance market and explores the role of high-performance, low-power data converters in next-generation LiDAR systems.The audience will gain insights into the critical parameters and requirements of a LiDAR receiver, including sensitivity, range, field of view, and resolution. It also discusses the challenges associated with optimizing the receiver's performance, such as reducing noise and increasing dynamic range.The presentation will address the functional safety and quality requirements associated with automotive standards. As LiDAR systems play a vital role in ensuring the safety of autonomous vehicles, they must comply with stringent industry standards and regulations.The next section of the presentation emphasizes the impact of high-speed data converters in next-generation LiDAR systems. High-performance, low-power data converters are essential for accurate and real-time data acquisition and processing in LiDAR systems. The presentation discusses the key specifications and design considerations for data converters, such as sampling rate, resolution, power consumption, and noise performance.The final section discusses the benefits of incorporating programmable Digital Signal Processing (DSP) hardware along with the data converters, particularly in terms of data rate reduction for IO transfers. Leveraging the power of configurable hardware, real-time processing of Fast Fourier Transform (FFT) and Constant False Alarm Rate (CFAR) operations is made possible. This enables the system to handle the vast volumes of sensor data swiftly, allowing for accurate and timely detection of objects in the path at longer distances, while simultaneously reducing data rates for IO transfers, thereby significantly reducing power consumption.In conclusion, this presentation highlights the significant contribution and impact of next-generation LiDAR solutions that leverage high-performance, low-power data converters. It showcases the motivation for LiDAR adoption, describes the role of LiDAR receivers, addresses functional safety and quality requirements, and emphasizes the criticality of high-speed data converters and on chip DSP hardware.

BeammWave develops disruptive system solutions for 5G and beyond, focusing on making digital beamforming for mmW efficient, with a mission to unlock the potential of mmW in user equipment. Development started in 2020 and spans from systemization to physical implementation, including Antenna, RFIC, MS-ASIC, Digital ASIC and BB algorithms. With the need for an efficient, manageable, scalable, and flexible development platform, BeammWave realized the potential in the Cadence Managed Cloud Service offering.

With the variety of EDA tools required to deliver a modern design, optimizing time to results for each workload can lead to better coverage and increased engineering productivity. However, some EDA workloads require faster CPUs, some depend on the RAM/core ratio while others require larger L3 cache.Using AWS, customers can find the optimal compute options to run their Cadence tools. In this live demo we learn how to improve time to results using better compute choices for your Cadence tool. We will launch be comparing 3 separate tools (Spectre, Xcelium, Clarity) and measuring the performance impact.

Working with a reliable IT infrastructure and design environment is essential for realizing System on Chips (SoCs) with high complexity. Such an infrastructure must not only provide dynamic performance scaling, but also offer multiple accounts to seamlessly cooperate with co-workers and other project partners. Furthermore, EDA tools, technology data and design flow must be integrated and maintained while ensuring compatibility and efficiency. Despite their importance, these time-consuming tasks come with substantial challenges that startups, SMEs, research institutes, and universities must navigate, potentially slowing down project initiation and compromising operational efficiency. Consequently, there is a growing demand for a modern and reliable infrastructure that can alleviate these challenges, enabling them to focus their efforts on driving innovation, conducting outstanding research, and pursuing their core objectives. With makeChip, an innovative Hosted Design Service Platform (HDSP), Racyics® offers a central gateway to design integrated circuits based on advanced semiconductor technologies without upfront invest in design environment and design methodology targeted for start-ups, SMEs, research institutes and universities. The platform provides reliable IT infrastructure with a full set of Cadence® EDA tool installations and technology data setup, i.e. PDKs, foundation IP, complex IP. It is built on top of AWS cloud infrastructure with servers located in Ireland ensuring high level of stability and scalability. All tools and design data are linked by Racyics’ silicon proven design flow and project management system. The turnkey environment enables any makeChip customer to realize complex System on Chips in the most advanced technology nodes. On top of all, access to Racyics ABX IPs for GF 22FDX® is provided for reliable and predictable ultra-low voltage operation down to 0.4V. In this presentation, the concept and structure of makeChip is outlined in greater detail and the unique benefits for academia, start-ups, and SMEs are explored. Furthermore, already realized projects, such as SpiNNaker 2, are presented and how makeChip helped to boost their development and tackled design challenges. Finally, an outlook on makeChip and ongoing discussions with the European Union on establishing an EU Design Platforms is given.

With an ever increasing complexity of analog mixed-signal layout design, NXP is constantly looking for automated and productivity enhancing solutions to apply to its current custom layout flow. The introduction of Cadence Virtuoso Studio IC 23.1 allowed NXP to identify several features that could positively impact specific aspects of its implemented analog and mixed-signal layout work. This presentation intends to cover new functionalities introduced by Cadence, where these functionalities will be applied and how they can enhance the work developed by layout teams within NXP. An analysis of the performance gain in Virtuoso Studio IC 23.1 will also be provided, where an overview of the runtime needed for common layout steps used within NXP will be detailed and compared to the previous Virtuoso releases. In addition, the presentation will also highlight the importance of the partnership between the NXP DE (Design Enablement) team and Cadence AEs/R&D during the USV testing for the evaluation, tests and deployment of the features. To conclude, this presentation will emphasize the positive impact of specific features of Virtuoso IC 23.1 in NXP Custom Layout Flow and the importance of the early access partnership between NXP and Cadence.

As supply voltages are decreasing to 1.2V and below in sub-100nm technology nodes, amplifiers with high gain can only be built by cascading multiple stages rather than cascoding/stacking.However, multi-stage amplifiers require challenging compensation solutions to achieve stability in feedback configurations.The stability of a feedback amplifier is assessed by means of the loop transfer function, out of which the phase and gain margin values can be calculated. An effective tool to obtain it is the stability (stb) analysis.This work discusses the proper setup and usage of the stb analyis in three-stage operational amplifiers with nested loops. A comparison of loop-based vs. device-based algorithms in stability simulations of three-stage amplifiers is provided.Three Nested Miller Compensated amplifier topologies are considered:- only with compensation capacitors (NMC)- with two nulling resistors (NMCNR)- with three nulling resistors (NMC-3R)The stability of the three-stage amplifier is based on amplifier poles of a 3rd order Butterworth frequency response in unity gain configuration. This leads to the sizing of the Miller compensation caps inside the nested loops.The analysis results show improved phase margin from NMC to NMCNR to NMC-3R and enhanced flexibility of the NMC-3R topology with the potential to optimize for power consumption, bandwidth, or figure of merit.

In today’s dynamic scenario, the design complexity is increasing significantly for analog mixed signal designs as the technology moves forward and the impact of process variations is becoming more and more significant to increase the unpredictability on circuit performance.

The matching approach has to be strongly used to make effective reduction on variations for  device’s performances, improve the layout quality and globally make products more reliable.

Modgens constraints are defined by frontend design to share the requested devices pattern with the backend layout engineer and be sure the constraint is applied for Design Review needs towards our customers.

In the previous Virtuoso framework, ModGen tool was the native automatic solution for placing large high matched structures in one single shot, but it was so uncomfortable when channels size has to change as native virtuoso commands cannot be used so users prefer to flatten Modgen to be at ease with modifications.  ST TR&D Smart Power has developed a capability to rebuild the Modgen constraint according to the one arranged by the layout placement and checking the pattern against the frontend one reporting if any change.

Virtuoso Studio 23.1 has made available a way to overcome the limitations and skip additional steps by giving the transparency to the modgen figGroup which allows any user to easily modify its row channels by staying on the canvas as for the other devices without the need to access its modgen dedicate environment.

The requirements for the components for safety-critical applications, like the automotive ones, are quite stringent: they need to be reliable under any condition in time and the whole design and verification flow needs to be traceable.

The use of a technology like “Setup Library”, already present within ADE, with the introduction of the “Verification Spaces”, to correctly slice the multi-dimensional results database (vs Montecarlo iterations, vs corners, vs variable sweep)  naturally built in ADE, together with added capability while reading and writing complex spreadsheet data, are the key elements that make Verifier Composite Requirements, recently released within the new Virtuoso Studio IC23.1, the missing tool to completely “automate” our flow.

In this paper we are going to describe how ADE Verifier fits our needs and correctly interacts with the other tools used in our overall analog verification flow, focusing on real databases generated, in Virtuoso ADE, while developing our automotive product.

In advanced node process the complexity of the design rules increases rapidly. We need a way to come to the result fast and easy to meet the time to market goal. Cadence In-design Physical Verification has a capability to proof the manufacturing rules based on the Pegasus signoff engine. The new integration and infrastructure in the Virtuoso platform enables the users to work intuitively within one environment. The fill mechanism as the requirement for DFM is also integrated seamlessly in this same new cockpit.

Accurate simulation of analog and RF design regions often relies on device and routing compact modeling, which means that parasitic extraction does not simulate R, L, C elements in these regions. But there are use cases when metal routing in such sensitive areas still need to be extracted by PEX for flexibility and design benefit. Dependent on technology application, there could be design regions where metal routing (usually on low BEOL levels) gets different correction (OPC) to improve the printability and/or device characteristics. This presentation shows how Quantus parasitic extraction solution can address region dependent OPC values for more accurate post-layout simulation.

NXP has a long history of delivering products to multiple markets with access to many diverse silicon technologies. The largest of the IC development teams were originally spun out from Philips and Motorola and eventually merged in 2015 as NXP Semiconductors. As part of this evolution, the combined company dealt with numerous IT and design system integrations and developed internal systems for capturing and managing IP design data, Product Lifecycle Management (PLM) and chip tape out management. While NXP had deployed these various systems to coordinate the management of design data and capture analog and digital design IP, the design methodology teams also saw a need to formalize a uniform IP publishing and reuse workflow. The goal was to streamline the steps for IP producers to make analog and digital IP available for reuse across all product teams and to enable IP consumers with a robust search capability so that finding IP was as easy as using any modern online electronic component web site. Several custom applications had been developed over 20+ years at NXP, but an easy to use search function with detailed filtering by IP classification, technology node and design parameters was not available. To provide engineers with the ability to find IP components and assess their compatibility to reuse in new projects, existing NXP data repositories would need to be extended to capture key IP properties (metadata) and augmented with Web based interfaces to enable a consistent and reliable search platform. Uniform requirements for IP publishing needed to be defined so that the user would be guided in completing those requirements so that their IP could be found and reused. An intuitive workflow was needed to progress the IP through multiple stages - from initial capture to published for reuse and tracing effectiveness of reuse.

The ever-growing complexity of silicon ICs, the evolution of the technologies, the need to correctly predict the performance of analog circuits in always more complex scenarios, force the analog designer to run a huge number of simulations, generating a big amount of data, with the need to easily access to them, to be on-time while taking crucial design decisions. A “smart”, “reactive” and “powerful” Analog Design Environment becomes a must, in a scenario where projects areas become crowded of data and users, with the need to concurrently access to simulation results. If the Virtuoso ADE infrastructure has been able, till now, to provide the needed “power” (e.g. Montecarlo simulations, with variable sweeps, hundreds of corners simulations, Functional Safety applications, design “check and asserts” functionalities) it is sometimes evident that the ADE UI suffers while trying to “control” the huge amount of data generated by hundreds of simulations ran in parallel, and, at the same time, offering responsiveness to the user that want to “work” preparing the next design step. For this reason, we looked with great interest to the new “distributed” functionalities offered by Virtuoso Studio IC23.1, with a new infrastructure able to keep the main Virtuoso process at the center, mainly focusing on its “interactivity” to offer a better user experience, but able to “delegate” to other processes the tasks related to the handling of huge databases: simulation psf databases, maestro results database and so on. This paper mainly focuses on our results while trying the distributed capabilities in the ST farm, testing them in the “complex” ST environment, characterized by many custom tools, with ADE able to interact even with other “EDA vendors” tools. Even if some “fine tuning” has been needed, the overall perception is that this new “distributed infrastructure” is a big jump forward: we observed significant enhancements in term of “GUI reactivity” both in the simulation phase and in the evaluation of the results. The new ADE environment looks faster, with a better memory management and more robust, even if some issue persists at the time of the abstract submission. Additionally, its capability to “reconnect” running simulations even after a critical situations like a crash or an unwanted closure, increases the design efficiency, without the need to “restart again” simulations partially done.

The presentation will talk about our collaboration with Cadence to develop a tool for layout review purpose which can be used to capture findings and their resolution in analog block and top-level layouts

Design Review (DR) is a tool which is supposed to be used in many TI projects

In it’s core part, the presentation will introduce the audience …

… to the evaluation path, benefits and problems of the tool

… to the improvements of the automation in terms of quality, intuitiveness and performance

… how the DR solution is planned to be integrated into the TI design environment front-to-back

… to convincing arguments why every project should make use of DR 

The presentation will end with a summary, including a forward looking statement

We used Virtuoso IC23.1.3 as part of the Early Adopter Program to explore three new features that shall increase verification engineers' productivity. At first, Large Scale Cloud Simulation (LSCS) was used to distribute netlisting and simulation jobs of our inhouse simulator to a high number of nodes. The changed architecture allowed us to make better use of our resources and to have better insight into execution status. The reduced load on the main Virtuoso instance allowed to designers to continue working throughout the entire run. We then enabled the separate storage of results and parameter values for Monte Carlo runs. By saving the latter into the statistic database, we significantly reduced the loading time for printing statistical parameters after simulation. Finally we used ViVA distributed plots to decouple waveform viewing from the main virtuoso session. This allowed us to submit the plotting job to another machine. The main virtuoso therefore remained responsive even for large result databases.

Virtuoso Studio provides many new features where we expect they will increase our productivity for full custom designs at Infineon. We want to give some insights and examples how these new functionalities will give support to deal with current and future design challenges.

Thermal simulations are becoming more and more relevant to Electromigration (EM) analyses. After Cadence introduced devices Self-Heating (SHE) in EM some time ago, we are now showing a novel method to take inter-device thermal coupling into account.   

Heat propagation can be simulated completely by means of an electrical simulator when introducing thermal coupling-capable device models and using thermal couplers. This approach avoids expensive 3D electro-thermal co-simulation and thus is applicable to larger analog circuits.

The session will show the complete EM analysis flow starting from a design, explaining how the PEX result is post-processed by automatically adding a thermal network and how it plugs into EM simulation engine.   

We close with a comparison of traditional Self-Heating against Inter-device coupling SHE results and will give correlation results with true silicon.

This work presents a functional and efficient design algorithm for the semi-automatic placement of common circuital components under predefined constraints, that improves further the layout activity experience in analog integrated circuits on CMOS and BCD technologies. The methodology of the automatic layout generation has the target to respect the state-of-the-art of layout engineering aiming also to optimize the labor effort. The algorithm relies on a first recognition phase that loads multiple design constraints and matching considerations which can be customizable by the user as input parameters; a set of design rules is provided by the user whereas matched structures are detected from the schematic view.

Design Finishing Pattern Optimization (DF-POP) is a tool for improving the chip yield. Layout patterns which are known as yield limiters are modified to get higher yield values. This results in a larger score of the Manufacturability & Scoring (MAS) deck. It has been demonstrated a yield gain in a single digit range which is significant.

The capabilities of analog circuit simulators like Spectre and computational speed are increasing. That makes the maximum size of analog circuit designs, which can be simulated in an affordable time, bigger and bigger. Moreover, with decreasing sizes of technology nodes, signals in transient simulations are getting faster. In order to increase the coverage of simulation tests, designers extensively use parallelization of simulation runs, which results in an explosion of the number of analog simulations. All these facts make the occurrence of convergence or speed problems in analog simulations more likely. Often this issue can be solved by re-setting simulator options or changing tolerances. But many times the root cause of a convergence problem is presumably inside a compact model. In this case, thousands of instances, using many different model cards or device sub-circuits are objects of investigation. A powerful tool is necessary that allows efficient analysis and debugging of model and instance parameter settings. Such a tool has been created with the use of the Spectre-Python interface and it turned out to be very effective.

IBIS (Input/Output Buffer Information Specification) model represents the Voltage-current and Voltage-time behavior of ASIC I/O pins, which is broadly used for IC vendors for use of high-speed board simulations to the customer. By using the model, it can detect the system error in early phase, reduce the cost of development for electrical system, speed up the design cycle.This talk is about the flow of IBIS model generation and validation by using Cadence tool Virtuoso/spectre and Sigrity IBIS modelling(T2B). The IBIS model version is 7.0 and the model is for automotive application.The model generation starts with pre-modeling activities: model requirements and conditions. In Virtuoso, I/O schematic, extracted view and netlist are the inputs to generate the model. In T2B, a template which includes IBIS version, operation conditions, pins information, model types, etc. are prepared. With the steps of Run spice test, Convert to IBIS model, Run Golden Parser check, the IBIS model can be generated according to IBIS format and standard.The model validation requires the definition of I/O load condition from the customer. In T2B, it can simulate and compare the IBIS model vs netlist with different load conditions. It calculates Figure of Merit (FOM) for the pass and fail in the validation report. Additionally, the flow also provides the validation in virtuoso to compare IBIS model with schematic/extracted views.For multi corners model generation and validation, there are python scripts provided to automatically plot IBIS curves and generate T2B template. The Batch-mode is also available to run multi-model conversion and validation.

The shortage of integrated development environments (IDE) for process design kit (PDK) implementation motivated to develop a code editor with extended functionalities. The modern editors and IDEs are largely non-optimal, as they do not provide PDK specific functionality and they are not embedded in the leading-edge electronic design automation (EDA) software tools. The presented IDE rEDActor addresses these problems and challenges and facilitates the effort required for PDK development. The presentation explores the use of IDE rEDActor to improve and accelerate the contribution of PDK source code. The IDE helped to reduce development time of PDKs for 0.13 um and 0.25 um SiGe BiCMOS technologies.

An early and accurate area estimation throughout the hierarchy is key for Bosch ASIC designers to conclude on die size and IO placement.This talk shows how Virtuoso Design Planning and Analysis (DPA) helps Bosch throughout the implementation process for new designs as well as for cases with significant block reuse.

With the increasing complexity of designs, advanced technology nodes, and physical verification tasks, in-design signoff quality verification is needed more than ever. Not performing the physical verification at an early stage leads to a conservative approach, wasting silicon area, or leading to a higher number of iterations of DRC during the design closure and an unpredictable impact of inserted metal fills. The unavailability of in-design signoff quality verification and metal fill flow make designers heavily dependent on signoff tools towards the end of design closure, significantly growing the length of the design flow, decreasing productivity, and increasing the Turn Around Time. Virtuoso Pegasus DRC and Fill allow the layout designers to run signoff quality DRC and metal fill insertion during the early stages of the design. Besides the innovative and comprehensive set of features available in Pegasus, the smooth integration of these features in the Virtuoso cockpit increases the users' productivity. The solution helps catch DRC DRC violations early in the design cycle and estimates the metal fill impact. This reduces the number of iterations and boosts productivity by a shorter edit–check–fix cycle. Layout designers stay inside Virtuoso thru their entire design cycle (Design + Physical Verification + Fill) without breaking their workflow.

This paper will connect system-level simulations for different design architectures with actual PnR PPA data for 2D design. We will see how increasing the memory bandwidth impacts PPA and how to mitigate that. We will further show the benefits of extending the design to 3D and performing a complete 3D PPA analysis. The results show that 3D can improve the performance, power, and area compared to the baseline 2D design.

With designs growing and TAT increasing with lower node geometries it quickly becomes a bottleneck for performing simple what-if trials for RTL fixes.This paper will present the challenges faced when you have large implementations with long run times but only need to focus on a specific piece of the implementation for RTL changes and testing.It allows the ability to simply model the physical stretching effect of communication/fabric modules when shaping the floorplan in a black box flow.The commands explored in this paper are from the Cadence Black Box flow which has been integrated into GPU teams block level implementation flow to enable focused implementation of a large design by black boxing all the other elements surrounding it in a quick and simple way.

We have recently taped out a chip in 28nm using Cadence implementation tools, viz Genus, Innovus, Conformal LEC & Conformal Low power. SoC implementation journey was full of excitement and posed challenges at every step. However we were able to overcome all the challenges and meet the given schedule. Some of the key challenging aspects of this journey are captured in this presentation.

To improve the runtime and the QoR of a Digital Physical Implementation Design, we have developed an entire implementation flow from the synthesis to the layout based on Cadence Tools.

Genus, Conformal, Conformal Low Power, Innovus, Voltus, Tempus, Quantus, Track-Based Metal Fill based on Pegasus.

MathWorks' MATLAB®, a high-performance programming and numerical computing platform used for algorithm development, and Cadence Stratus™, a high-performance high-level synthesis technology, are both industry-leading solutions. Cadence and MathWorks have developed an integrated flow to estimate hardware PPA (power, performance, area) at the early stage of algorithm development in MATLAB by generating synthesizable SystemC and performing high-level synthesis with Cadence Stratus. In this session, we will introduce this workflow showing a real example.

Modern vehicles are equipped with multiple cameras, which provide a vast amount of real-time information about the environment as well as of the interior of the vehicle and the driver/passengers. To process the data an Image Signal Processor ISP like the RPP from Dream Chip Technologies is required as well as a NPU like the NNA110 from Cadence. The RPP does the real time image processing like Bayer pattern de-mosaicing, white balancing, local tone mapping, conversion to special machine vision formats and many other functions. The processing after image processing is usually done with deep neural networks that are accelerated by AI engines like NNA110 from Cadence/Tensilica.The NNA110 and the automotive 20 MP dual RPP have been integrated in the latest automotive SOC developed by Dream Chip Technologies in 22FDX. It is targeting the application described above by supporting up to 16 Cameras and includes additionally a dual ARM A65AE with 1.2GHz, DCLS ARM R52, PCIe G3, MIPI Rx and Tx. The total AI processing performance is 10 TOPS (INT8). The NNA110 is running at max. 950 MHz and features 3.8 TOPS.With the new Cerebrus AI based solution Cadence promise better PPA results than the standard manual approach. We used NNA110 and the RPP blocks out of the latest Dream Chip 22FDX SOC to evaluate Cerebrus. We will compare the max. frequency in typical and worst case corner, area and as well as power.We will compare the PPAs between 22FDX and N7 as well as Cerebrus AI based vs. manual standard approach.

With the hierarchical digital implementation of complex Systems on Chip (SoCs), the area between the computing building blocks like processors, accelerators, and system interfaces remains reserved for SoC data transfers. Network-on-Chips (NoCs) have emerged as the solution for top-level on-chip communication and have become the long pole for timing closure. They have seen a rapid rise in protocol complexity for coherent and non-coherent designs and flows for NoC IP Development - automated RTL generation from high-level configurable topology descriptions - have optimized development productivity over the past two decades. With RC wiring delay dominating transport delay, changes in the NoC topology caused by difficulties in timing closure during the Place and Route (P&R) phase can add significant project delays if the NoC architecture needs to be changed to accommodate timing aspects. This presentation will outline a flow and methodology that automates the connection between NoC architecture development and digital implementation using .lef/.def datasets of floorplan information. It will illustrate how estimates based on abstracted technology information make NoC-topology development aware of physical timing and how automated export of placement guidance and constraints to Genus/Innovus-based digital implementation avoids late surprises in timing closure. Based on a customer example, we will show how the digital implementation phase of NoCs can be reduced by up to 5x.

In the current design approach, the synthesis and implementation are often treated as two separate worlds. This distinction can lead to a cumbersome process where the multiple iterations that are often necessary between synthesis and implementation become an error prone development, due to the numerous communications and file transfers necessary.Thanks to Genus, we are now able to integrate the physical synthesis smoothly in the implementation flow, taking advantage of the converging points with Innovus along with the common UI.The addition of Genus in the implementation flow allows for both tools to work in a more optimized way, utilizing the common database to pass information from Genus to Innovus, as well as taking into account implementation considerations such as the floorplan starting from the synthesis. This provides a seamless flow able to converge faster and more efficiently, while keeping open doors for customizations. In this presentation, we will expose the experience of ST Microelectronics with the integration of Genus in the ST TR&D implementation kit, making use of the common settings and convergence of setup between the two tools such as the reuse of the MMMC, scenarios and other setup files to lower runtime and transition hassles.

Due to the body biasing feature of the GlobalFoundries 22FDX+ technology a very high number of different corner scenarios for library characterizations exist. The challenge is to select the right scenario to implement a specific design at the Minimum Energy Point (MEP). Currently the scope of this kind of design space exploration is limited by a low number of existing PVTBB library characterizations. Extending this design space by adding additional characterization points is not feasible due to high NRE costs of each characterization campaign. There for a low effort methodology was developed, which allows an MEP search for arbitrary designs within a wide design space without the need of library re-characterization. The basic concept of this methodology is to determine timing and power derates for potential PVTBB scenarios based on a 22FDX+ ABB model. These derates will then be applied to a full Cadence RTL2GDS flow based on an existing PVTBB library characterization to analyze the potential impact on PPA and to determine the MEP scenario for the specific design. This presentation will cover the developed MEP search methodology and the results of an MEP search study for a state-of-the-art MCU ULV implementation in 22FDX+.

An analog-centric design integrates small to medium amounts of digital logic, to support and control big analog IPs: in such kind of designs, a schematic-driven flow with an Analog-on-Top methodology is usually applied. Verification task in an Analog-on-top methodology includes different steps: 1. Analog IPs verification 2. Digital IPs verification 3. Analog Mixed Signal TOP verification Traditionally, one sub-part of digital on top designs verification step is the connectivity checks, performed using the Jasper Connectivity Verification App (CONN) provided by Cadence. This paper discusses how these techniques, used in digital on top designs, can be applied to extend connectivity verification in the analog on top designs using Analog Mixed Signal (AMS) verification environment. This innovative approach allows us to: • Reduce the simulations time: checks with Jasper Conn are static and faster than simulation regression. • Avoid specific simulations created specifically to check the connectivity. • Automatize the checks (with a Jenkins platform, for example). • Discover connectivity bugs before that the top AMS simulation phase. • Avoid the use of SVRN models that must be equivalent to analog block behaviour. • Use the top-level netlist extracted directly from the schematic, so major accuracy and reliability. With this methodology we were able to find some wrong configurations of GPIOs of the device. For example, a TestEnable pin was erroneously forced during scanmode, in fact the pin was an input as for documentation, but the pad was configured as output. This was not even noticed with standard mixed signal simulations because stimuli were applied to GPIOs using an ideal generator, so simulation was passing, only by looking at current consumption on GPIO, the problem could have been seen also in simulation.

When an OOMR is used as a probe the datatype for the assigned variable must match that of the OOMR. The OOMRmust also use the correct access operator to retrieve the specific field of information. This alone can cause issues since V(OOMR) is not allowed in System Verilog but needed for probing Votlages. Certain OOMRcan be supported via conversions using A2D/D2A's. However, with the use of User-Defined-NetTpyes (UDN's) this becomes more complex since these are structures that can use a mixture of logic, real and integers. If one wants to write a testcase using digital models, then subsequently run the same test with the transistor design any OOMR will not work in both using LRM constructs. To work around this limitation the VPI allows users to write C functions that access the internals of the simulator and return values. Using this approach, one could write a generic getVoltage/getCurrent function that will work whatever the abstraction of the path is.

Our company, NXP, is delivering  products that  meet customer demands with commitment to quality, fast delivery , and reliable products, as frontrunner objective, on top of our multiple solutions and recommendations to our customers.

With the increasing demand in advanced and complex IC designs with focus on mm-wave RF strategies, the IC-packaging is also evolving.

With consideration to the complexity of each levels/hierarchy, NXP, together with Cadence,  evaluated, adapted and tailored Virtuoso Multi-Tech (VMT) Solution to match NXP requirements on IC packaging.

The Virtuoso Multi-Tech Solution supports several packaging types (e.g. flip-chip and wire-bond, side-by-side) with surface mount device components and mmWave structures.

The IC-to-Package interface can now be mainly done in Virtuoso-RF infrastructure where IP, SOC and Packaging designs can be integrated. Optimization of designs can now be easily achieved while avoiding many error-prune cycles of design translation and transfer to other platforms.

Some of the interface that can be found in Allegro® ADP+/SiP are now integrated in Virtuoso-RF that can be used in constructing multi-fabric designs in all phases of planning, implementation and verification.

The overall presentation shows the challenges that we faced in design conceptualization, communication and integration and how Virtuoso-RF solution helped defining resolutions and enabled efficient and reliable way-of-working that led to an excellent output welcomed by our customers.

This paper talks about smart innovations in AMS DV to improve simulation turn-around time by improving simulation run-time of mixed-signal co-simulation, which is the majority of the time, especially with complex SoCsSwitching circuitry and/or high-speed clocks generate a large number of events where the analog simulator has to perform the calculation resulting in the slowness of the simulationsThe high-speed clocks can originate in blocks like oscillators or PLL and traverse through hierarchies and digital cells before reaching the analog boundaryIn this process of traversal, it generates an equivalent high-speed signals tree, which has a significant impact on the run-time of mixed-signal co-simulationsIdentifying the digital cells or common blocks and replacing them with the faster behavioral models can reduce additional time-events to the cosim and increase the simulation speeds effectively without losing accuracyTracing these replaceable networks in multiple complex hierarchies of the design is a tedious, error-prone, and challenging task and requires significant manual efforts, as a single cell miss in tracking can slow down the simulation or unnecessary cell replacement can lead to wrong resultsAutomated Net Tracer [ANT] tool utilizes net traversal technique using schematic design database selectively tracing cells in high-speed clock trees, recording the hierarchical paths of it and autogenerating the config/amsd files to replace these cells easily in any DV workflow

This presentation going through Cadence Allegro X Design platform, From schematic to layout and simulate. There will be a small demo.

Perform SI and PI analysis in the background of PCB Design software. Easy to use like a spell checker.

Identify and avoid temperature problems in electronics development at an early stage. Efficient design development through electro-thermal co-simulation. Presentation features application examples using Celsius PowerDC.

Designing a 2.5D heterogeneous integration platform involves integrating multiple dies onto a silicon interposer, requiring efficient signal and power routing. Signal routing minimizes delays, crosstalk, and ensures reliable communication, while power routing delivers stable and sufficient power. Electrical performance analysis assesses signal integrity, timing, and power distribution. High-speed interfaces demand optimized routing for impedance control and transmission line effects. Sign-off involves verifying interconnects, signal integrity, power integrity, and timing. Advanced simulation, electromagnetic analysis, and physical design verification are employed for validation. Collaboration among design teams is crucial for successful integration and reliable operation of the 2.5D heterogeneous integration platform. This increased collaboration brings with it challenges and risks. During the design, Cadence Integrity 3D-IC software was used to mitigate these risks and design implementation. Verification was done using Voltus and System LVS.

Products and services across all industries are increasingly interconnected and intelligent, enabling consumers, citizens, workers and patients to unlock more personalized, engaging experiences that improve quality of work and life. In this dynamic context, companies must rapidly develop electronic systems that are safe, high quality and right the first time. Mastering electronic system complexity and cost/time-to-market pressures requires collaborative innovation that unites electronics, mechanics and additional functions across the value chain.

In case a package RF simulation is done within an external tool, it must be ensured that the Via positions will be located 100% properly. AutoCAD will be an example data format for exchange. Due to the fact an import won't reflect the coordinates in detail, a small workaround will be required. The Cadence functionaility "Compose Symbol from Geometry" will be use to visualize the apd stack symbols of a Via on the right location.

This paper focuses on the integration of SystemC with PSpice, by allowing the simultaneous simulation of the digital and analog behavior of an electronic system, providing a complete and accurate overview of its performance. The presentation will cover topics like configuring and connecting components, creating a co-simulation model, as well as interpreting the results obtained. As electronic systems become increasingly complex, it is important to accurately simulate their behavior. This requires a combination of analog, digital, and mixed-signal simulations, which can be challenging to perform using traditional analog simulation methods. Co-simulation with PSpice and SystemC could provide a powerful solution supporting complex simulations systems using both analog and digital models. By integrating these two simulation environments, users can leverage the strengths of each tool and accurately model the behavior of complex mixed-signal systems. The new Infineon Automotive Smart Power Switches are providing protection functions and enhanced diagnostic capabilities. The device offers an adjustable current limitation to offer higher reliability for protecting the system. In case of a short circuit to ground the PCB traces, connectors, as well as loads, can be protected. Furthermore, the device has a capacitive load switching mode implemented to charge capacitors. Having all of this in mind we developed a analog behavior model using PSpice and SystemC. In our example, creating a model containing a complex finite state machine to handle all the function of the device could be a challenge using circuit level implementation or Spice and analog behavioral modeling methods. While PSpice is a powerful simulation tool, it is primarily focused on analog circuits. In contrast, SystemC is specifically designed for modeling digital systems and provides a more intuitive and efficient way to create FSMs. Using SystemC modules we can avoid convergence issues generated by the digital hazards, also the simulation time improves significantly. The seamless integration of different modeling techniques into a single environment and simulator has been a significant advantage in overcoming the challenges of simulating complex mixed-signal systems. This has been demonstrated through the integration of SystemC with PSpice, which allows for the simulation of the behavior of such systems in a more efficient and accurate manner.

How to save time and effort in optimizing a differential pair via transition from one layer to another using Optimality Intelligent System Explorer.

Antenna design must adapt as IoT devices continue to change our connected surroundings. Ignion's innovative Virtual Antenna technology offers a path forward. This work, distinguished within a university master's project, harnesses the capabilities of Cadence's AWR Microwave Office Network Synthesis wizard to design a successful matching network for a Virtual Antenna®.The Network Synthesis wizard provides a systematic process for impedance matching that is both user-friendly and powerful, ensuring an optimal matching network for IoT devices. This study embodies these capabilities, detailing the design of a matching network for a 131 mm x60 mm IoT device. Our research highlights the adaptability and effectiveness of Ignion's Virtual Antenna technology in fulfilling the strict dimensions requirements present in such compact devices.Our multiband matching network consists of six lumped components: three capacitors and three inductors. In conjunction with the antenna booster, this network delivers excellent adaptation efficiency across all bands, achieving a reflection coefficient below -6 dB in the whole band of 0.824GHz-0.965GHz and 1.71GHz-2.69GHzThis endeavor exemplifies the synthesis of academic insight and industrial innovation, leveraging Cadence's AWR to manifest Ignion's vision of efficient, flexible, and high-performance antenna solutions for the IoT sector.

Massive MIMO is intended as the major success factor for 5G cellular communications. However, the MIMO infrastructure at the critical sub-6GHz band, and particularly the radio unit Bill of Materials (BOM), needs further optimization, in order to reduce the costs substantially and allow wider adoption. The reduction of the number of RF components is crucial for packing a high number of radios in a single radio unit. Integration of the RF components in a smaller number of IC packages or even a smaller number of dies, presents various difficulties because of the induced noise and the increased heat dissipation of the more densely integrated circuits. In this presentation, a circuit design of multiple PA drivers on a single die using the GF-22FDX CMOS-SOI technology is presented. Two versions of the circuit are included, one with two drivers and another one with four drivers. Guard bands alleviate problems related to crosstalk and interference due to congestion, at the cost of an increased area so, careful optimization is required. The EMX 3D Planar Solver was extensively used for circuit optimization. The resulting unique design of the 4-PA drivers delivers a peak power of 28 dBm per driver with 32% peak PAE. It can replace four discrete driver ICs, reducing the total number of key components in a 64T64R radio unit by more than 15%.

Since 2014, the Portable Stimulus Standard (PSS) has had a significant impact in the microcontroller division in terms of improved Verification productivity, schedule and quality. In the division, the System Level Notation language (precursor to PSS in Perspec) is what is used. The transition to PSS is slow but certain.The first focus for the MC division was to create a set of PSS driven Verification models, which can be combined to stress test a complex, Real Time Cluster with the help of Perspec. This multi_cpu_stress project will be explained from the modelling perspective and will highlight the challenges encountered whilst trying to create these sophisticated runtime scenarios. With multiple SLN models and scenarios available, another challenge was to ease the Test Selection and Categorisation for the Verification Engineer running regressions at the Cluster and SoC levels. This was achieved by using simple Tables in Perspec. The tables represent definitions of action/component attributes as well as values or ranges used in conditional constraints depending on the configuration, model or scenario being run. The deployment of the multi_cpu_stress scenario was successful and is in use on different Testbench levels (vertical reuse – SubSys, SoC), platforms (horizontal reuse – Simulation/Emulation/Silicon) and product families (lateral reuse – Second generation Derivatives, third generation Derivatives). Currently, what has been learnt from the deployment of the multi_cpu_stress scenario is being used to build new models and scenarios for the Verification of an Advanced RADAR SoC where specific use-cases have to be modelled with Perspec under SLN/PSS.The following topics will cover all the above: 1.Stress testing a complex, Real Time Cluster in Perspec – multi_cpu_stress 2.The Verification of Advanced RADAR SoC use cases using Perspec 3.Test selection and categorisation using simple Tables in Perspec.

This presentation outlines the innovative utilization of the Cadence Palladium hardware emulator for power estimation in a complex System on Chip (SoC) for Artificial Intelligence (AI) applications, designed by STMicroelectronics. The chip, with hundreds of clocks, involved collaboration from various teams - backend, RTL design and verification, architecture definition, software tool development, application development, and verification and validation platform setup. A crucial task for a design architect was to provide early power consumption and performance estimates. However, power results varied due to dependencies on factors such as clock frequencies and AI model compilation results. Additionally, optimizing power was challenging due to the unavailability of the HAL for clocking scheme control in early stages.

A flow has been set up that, within a reasonable timeframe (a few hours), extracts the necessary data for the final power consumption simulation on a full microcontroller executing complete AI inferences. For each run, it also extracts and keeps track of the main clock frequencies and high-level metrics, by exploiting both the Dynamic RTL and the embedded Logic Analyzer features of Palladium. The use of Dynamic RTL was key to avoid appropriation of the full system compilation process performed within another team. For the design architects, this comprehensive approach provides a unique method for power estimation, offering essential insights for the development and evaluation of complex AI SoCs.

One of the challenges in digital verification planning is the need for many test regressions to stimulate and verify a wide range of operating scenarios. However, this can lead to a large number of tests, resulting in longer runtimes for each regression. How can we reduce the number of random tests while maintaining the same level of coverage and quality, so to speed up the regression runtime Cadence Xcelium Machine Learning solution is a framework that takes control and coverage data from a design and testbench to generate a Machine Learning model and accelerate regression performance. The generated model is created by learning from iterative regression session runs and this model is then used to produce an optimized regression based on set criteria. Starting from two regressions already launched with Cadence Xcelium, Machine Learning was applied using Cadence Xcelium ML. In this paper we compare how original regression performance and results differ from the optimized regression in terms of number of test, runtime, overall coverage.

In order to ensure the correctness of a chip’s operations, Top-level connectivity verification at the IP Cluster or System on Chip (SoC) level is required. However, attempting to cover every scenario at the Top-level can be an overwhelming task for verification engineers. Typically, simulation patterns for the entire chip or IP Cluster are a subset of all patterns, with focuses on checking the integration of features among constituent modules rather than covering all simulation patterns of the chip. As a result, identifying corner case bugs becomes challenging. To address this issue, formal connectivity verification offers an exhaustive verification process capable of uncovering all possible incorrect connectivity behaviors. This paper outlines the experience of utilizing the formal connectivity tool from Cadence (Jasper), to streamline the verification process, reducing manual efforts and runtime. Additionally, integration of the formal connectivity tool with the Test Suite and coverage collection tool from Cadence (vManager) was established and the result was then eventually used for verification sign-off. The approach showcases an automated process for establishing formal connectivity checks at the IP Cluster or SoC level, eliminating the need for manual intervention, while providing coverage metrics necessary for verification sign-off. By optimizing this process, a significant reduction of the overall turnaround time was achieved, completing the verification cycle within a few days instead of months. The design has ~13000 Top-level and Inter-IP connections that require verification and the initial iteration of adopting this flow had an overall effort of 8 weeks including ramp-up and implementation which after optimization of tools and flow was reduced to 1 week of effort in succeeding projects. Infineon has successfully integrated the Cadence-provided integrated solution into the regular verification flow and have successfully used the flow for four distinct projects.

When we verify a System on Chip (SoC), there are different steps of verification to get done, to have a high score of both code and functional coverage. The top-level verification remains a huge effort task that requires a lot of resources necessary to get a working SoC at the first silicon. In the SoC verification flow we assume that all the integrated IPs are 100% verified at block level. Then at top-level we are going to verify: 1.IP integration: -We check that all the IPs are correctly connected on the bus and accessible by the masters of the bus matrix - This allows us to catch connection bugs 2.IP operation: We check that all the IPs are functionally working fine in the SoC. We configure and use any block of the bus matrix. This also permits the verification of the connection with IOs and others system resources like interrupt controller and security This allows us to catch system connection bugs 3.System behavior: - We check that the main application is working. Some tests are developed using more than one IP emulating a simplified version of the application - This allows us to catch system bottlenecks and system bugs About all the steps above, the tests are usually developed in C code (executed by the master CPU) and UVM test bench. The paper is focused on step 1; the idea is to use the Formal Verification to prove the IP integration. Internally developed Python utility generates specific SVA assertions by a simple SoC description excel file. It produces read-write properties that check the accessibility of the peripheral registers and memory spaces from the CPU bus master.This innovative approach allows us to verify the SoC integration early in the flow, with no need of any UVM test bench; the bugs commonly discovered are: -Wrong memory map-Wrong data bus connection-IP clock and/or reset stuck-atThe setup of the verification environment is faster than any UVM test bench and it can be reused for others Formal analysis such as CDC (Clock Domain Crossing) and Connectivity check. The main task is the definition of clocks, reset and functional mode SoC setup. This can take a few days compared to weeks for dynamic simulations. The Formal approach uncovers quirky bugs and reduces verification effort, even when applied at SoC level.

Neural networks are developed independently of their execution platform. On a microcontroller (MCU), they can be implemented in software but we develop dedicated hardware for higher performance. Then we need to make many architecture-related measurements and decisions: interface, bus structure, hardware functionality, design size and system performance. In the traditional MCU design approach, we use spreadsheets, simplified models and simulations: that is usually sufficient to determine the architecture that meets the system requirements. But the neural network accelerator performance is very sensitive on multiple parameters which are not easily abstracted. Cycle-accurate and bit-accurate simulation of many configurations is mandatory. That can be extremely long: running an inference of a very simple neural network takes 17 hours on a RTL simulator, and much larger networks need to be analyzed too. This approach does not scale for an exhaustive architecture exploration. Hardware acceleration on Palladium was the key solution to make faster simulations . After proper configuration of the design and its testbench for emulation, we reached a 2000x acceleration factor, which opened a new field of possibilities for the architecture exploration and optimization. After the initial setup of the emulation platform which produced basic performance figures at a satisfying speed, we enriched this environment with the performance tools of SystemVIP: STG to automatically add multiple non-intrusive performance monitors, SPA and SVD to process the data generated by the monitors. That produced detailed performance measurements, such as throughput and latency, per interface and per path. After the optimization of the accelerator and its immediate environment, we had to validate the performance in the context of the full SoC. Additional IPs drive more traffic and share memory access with the accelerator. We can either add existing RTL IPs, or create performance model of IP to inject the traffic in the SoC. For a camera pipeline, we used the capability of AXI AVIP to support directly the ARM AMBA Adaptive Traffic Profiles (ATP) to implement the model. This architecture analysis platform has been successfully used throughout the design of the SoC. All the tests written for architecture analysis of the neural network accelerator have been easily ported on the full SoC within a day, and contributed significantly to the full pre-silicon performance validation of the SoC.

Over the last decades a lot of improvements were developed to address the ever-growing challenge of functional verification, included automation, methodology, verification-Ips and more. A key metric for sign-off is coverage, the formal affirmation (qualification) that a certain verification step has been accomplished. While coverage is used to rate the stimulus generation completeness, there is still one missing part: the qualification of the Testbench (TB) itself – the answer to the question: „Is the TB complete? Do the checkers really identify all erroneous functions in the design?“. The demand for TB-Qualification is increasing with growing design complexity and new standards, e.g. the Functional Safety ISO26262 standard. This paper shows, that a state-of-the-art TB-Qualification can be executed using the Cadence Verisium Manager Safety solution, addressing three critical aspects of a TB-Qualification task: 1. integration into the customers verification environment (same tools, same look and feel), 2. highly optimized fault-injection campaign execution and 3. support of the manual analysis step through pre-classification and integrated debug solution. The feasibility of the solution was evaluated by several customers. Some of the results will be presented here.