CadenceLIVE Silicon Valley – OnDemand

As the complexity of SoCs grows, so does the complexity of their contributing IPs and the structure of the teams that design and verify them. This complexity has lead to an ongoing increase in the amount of resource and time applied to debugging failures at the SoC level. This presentation reviews the application of the Verisium AI-Driven Verification Platform and it’s AI and ML features to debugging regression failures in an automated way at the SoC level.

AI processing at the edge is becoming pervasive across embedded devices and products, ranging from on-device AI in a tiny form factor such as TWS earbuds and smart watches, to home electronics and appliances, to (semi-)autonomous vehicles. There is large range of the processing capability required for the large range of products and applications incorporating AI, with common themes of ease-of-use and delivering performance in a low-energy profile. This presentation will discuss the Tensilica IP products, including their accompanying software ecosystem, offered to SoC customers and partners to deliver best-in-class on-device and Edge AI solutions.

Shortening design period is one of the most important theme for designers. We need to keep duration of development or shorten it, even design scale becomes bigger rapidly.

Big Data Analytics has a big potential for it. We're always struggling for debugging design, and that's the biggest portion of design duration. We always have significant data, but it's difficult to analyze. It's too huge. It likes finding gold in the river. We know there are many treasures, but we gave up to find it.

JedAI is very powerful tool for finding big treasures from significant data pool. We can expect not only shortening debugging time but also finding it in advance. It means JedAI can shorten not only debugging time but also waiting time. How long do you wait for finishing P&R job in one design project? If you can shorten it, how effective? You can easily imagine the potential of JedAI.

We'd like to introduce the approach for shortening them and the latest status in our Automotive SOC and MCU designs.

Electronics design is undergoing a revolution as semiconductors are used in more and more market applications. AI is showing promise for addressing the growing complexity, finding optimal design outcomes, and substantially improving overall team productivity. During this session, we will explore how Cadence is using AI to address intelligent system design challenges, and what AI can deliver in the future.

Closing timing and finding the optimum balance of power vs. performance can be very challenging with the process technologies available and the complexities of certain designs. In addition, it can be difficult to remember all the tool settings and steps necessary to reproduce a particular flow result. There is a need for an automated way to try many different tool settings on a certain design and then retain the best run. Handling a task like this on a compute server farm is advantageous. This session will show how Cerebrus was used across ten different servers to find an optimum collection of settings to obtain the best result for a test chip. It will illustrate how Cerebrus controlled a flowtool based flow to derive numerous scenarios until finding the one with optimum results. Then the use of the saved settings from the best scenario will be used to reproduce the results outside of Cerebrus.

The EDA and ATE environments have always existed in different worlds. Increasing complexity of devices and the rapid acceleration of release cycles has forced us to challenge this paradigm. It is no longer acceptable to take months bringing up initial silicon and the problems that arise cannot go through repetitive cycles of debug. Large amounts of data must be retrieved from a device under test and sent to the proper tools to diagnose failures quickly. In this presentation, Teradyne and Cadence will discuss their collaboration to help tackle these challenges with innovative solutions.

Leveraging long-standing industry leadership in Ethernet, Broadcom offers solutions for a wide range of applications including data center infrastructure, service provider and enterprise networks. Broadcom continues to lead this space and is always looking to improve design flows to achieve best performance with reduced time to market. In this Session, we will talk about how we adopted Cerebrus machine learning tool to optimize power in our most critical blocks.

As design teams continue to adopt Cadence AI technology such as Cerebrus AI design optimization, and Joint Enterprise Data and AI (JedAI) Platform, the Cadence R&D team are busy developing exciting new innovative features for the future. During this session, join Dr Venkat Thanvantri, the Cadence R&D lead, to gain a deepdive insight into current Cadence AI capabilities, and ongoing development projects, such as AI driven data analytics for rapid design analysis delivering better power and performance results.

This paper focus on using the principles of PowerFirst by adopting the Flex Htree, Pmin 2022, and Cerebrus ML technologies to apply towards the problem of Dynamic Voltage Frequency Scaling (DVFS) Optimization on a recent Arm mid-core CPU. The outcome would ideally be trade-off analysis that captures various optimization points across the DVFS spectrum. The scope was determined by practical considerations like capacity, runtime.

The end goal was to reduce design exploration space and converge faster towards generating PPA target goals. As part of this project, we went through a 4-phase approach outlined below on a recent Arm mid-core CPU:

i. baseline

ii. baseline with Htree,

iii. baseline with Htree/Pmin and

iv. Cerebrus with Htree/Pmin flows

We started with understanding the OD (Overdrive) curve with a Pmin style build and validated the headline frequency, after understanding the power vs frequency curves at other domains,  we aggressively optimized for power at other voltage domains, and finally recovered any OD headline frequency perhaps at some power cost.

This flow will help multiple Arm groups (CPU/GPU/Systems) to have a common methodology that can enable future projects to accurately set and predict PPA targets faster.

Microchip is a leading total systems solutions provider in high performance microcontrollers and microprocessor solutions, communication solutions in wireless and wired connectivity and storage solutions with NVM and flash memory technology. With increasing demand for more functionality, shrinking dies and advanced nodes, chip design task is more challenging than ever.  At Microchip we are looking for new solutions/features to improve our design methodologies for better turn-around-times and PPA. Since Cadence Cerebrus Chip Design optimization solution claims better performance and power with improved efficiency of engineering manpower, we evaluated Cerebrus on designs from N6 TSMC devices and benchmarked against our internal BIC design methodologies. In this session, we will talk about our learnings about different use models of Cerebrus tool and benchmark data from our qualification work.

The problem of optimization is long-standing in the design field. For years the most conventional approach was the brute-force method of running parametric sweeps on the design space. But as systems become ever more complicated and the number of parameters increase, the computational resource and time cost becomes unsustainable. With Cadence Optimality Explorer, users are able to explore the same design space in a more efficient and intelligent way. By leveraging artificial intelligence/machine learning technology, Optimality removes the need for exhaustive sweep and dramatically reduces the number of iterations required to converge to the optimized solution.

Canon is a multinational corporation and world renowned leader, holding a significant position in the field of high quality CMOS image sensors. With Canon's corporate DNA of emphasis on technology, we are always looking for ways to improve design flows to achieve best performance with reduced time to market. In this session, we talk about how Canon used Cerebrus Machine Learning Chip Optimization solution to improve PPA by pushing power and timing and to find the optimal floorcheck at block level by using Cerebrus FP-Opt feature along with reduced engineering resources.

In the presentation we will present the implementation of an algorithms to realize a 4D automotive radar. As first different algorithms are compared regarding there usablility for a Tensilica implementation. After the comparision the best usable algorithm is implemented on the Tensilica DSP. Also additional TIE implementations are used to speed up the algorithms.

While some companies debate whether to go to the cloud, Groq's internal development infrastructure is rooted in the cloud. Our unique approach to building Groq chips requires a careful orchestration of multiple automated flows.  As a result, we integrate software factory principles into our hardware design. Groq will share how relying on cloud to design our chips and extending proven best practices in software engineering to hardware implementation turned our lean design team into a powerful design house for advanced nodes.

At Arm, we have taken multiple approaches to getting to the cloud, focussing in certain cases on time-to-migration and in others on cloud-native optimisation. In this session, we will outline the approaches we have followed while updating our compute estate to deliver a hybrid on-prem/multi-cloud platform. We will also talk about the benefits in terms of cost, performance and productivity that this migration has enabled from being able to run EDA tools on high performance AArch64 instances in the public cloud.

Advanced semiconductor applications, such as artificial intelligence and machine learning (AI/ML) and graphics, are fully leveraging dense advanced-node technology to push the extreme limits of design size. Physical verification on large digital designs traditionally requires significant compute resources for long periods of time (days), demanding high-performance CPUs and large amounts of physical memory.

In this presentation, the TSMC + Cadence + Microsoft collaboration for physical verification using the Pegasus Verification System highlights the GigaScale cloud strategy.

The talk will feature Cadence’s Pegasus physical verification signoff tool showcasing TrueCloud, FlexCompute, and the CloudBurst Platform, as well as Microsoft Azure’s latest virtual machine offerings suited for Pegasus workloads.

Design teams are constantly under pressure to tape-out chips faster. Advanced node technologies are not making things any simpler. As we move from 7 to 5 to 3nm designs, the number of checks to validate a design is increasing substantially. In addition, the checks themselves are getting more complex. These factors are resulting in longer validation cycles-- prohibiting timely, high-quality tape-outs. Design teams are looking to engineering IT to help with quicker turn-around time for their jobs to meet stringent schedules.

Shrinking process technologies are pushing the boundaries of verification infrastructure requiring engineering IT to grapple with 'cost-optimized' versus 'designer-efficiency optimized' infrastructure deployment. Unfortunately, neither choice is ideal. AWS, along with Cadence, is helping the design community overcome these challenges by leveraging AWS's virtually infinite compute and storage capacity. The elasticity of AWS helps address this demand curve by eliminating the need to choose between cost and efficiency. In this session, we will present various AWS technologies to expedite silicon design and achieve faster tape-outs. We will also present customer anecdotes of how organizations have successfully leveraged the scale, speed, performance and agility of AWS to reinvigorate their silicon design methodologies and shape the next generation of design engineers.

Get ready to leverage cloud to bridge compute capacity gap, elevate verification efficiency and accelerate Turn Around Time (TAT) for your next-gen design. We’ll share the unprecedented scalability and ease of use of Cadence’s cloud solutions including the Dynamic Duo - Palladium and Protium cloud - to power your next design masterpiece.

WD is a large enterprise with several data centers. WD has many services for their end customers in the Cloud (e.g. WD MyCloud) that connects the personal storage devices to the Cloud. However, internally, we had yet to do more semiconductor engineering in the Cloud. We embarked on this journey few years ago and are beginning to see the fruits of this effort. Significant portions of WD’s verification regressions are now ported into the Cloud.  There were many major hurdles in this effort in the infrastructure side (e.g. connecting on-site network and storage to Cloud provider’s infrastructure), and several in the EDA flows (e.g. queuing system, orchestration related issues, etc.). This presentation will outlines key challenges that WD faced in this journey, and provide some suggestions that may be helpful for other companies. The presentation will also talk about the business case and how that can potentially improve the business-case dynamic.

With low-power high-performance chips being today's norm across applications such as storage, memory, interface, display, battery management, etc., Power Management Integrated Circuits (PMICs) have become crucial part in today’s System on Chips (SoCs). Regardless of the application, a PMIC would consist of the following blocks at the bare minimum: One or more buck converters or switching regulators, a high-frequency oscillator (HFO) to generate clocks for triggering the digital logic, one or more low drop out (LDO) regulators, and some housekeeping circuits such as reference voltage and bias current generators, IO cells, pad rings, ESD protection circuits, etc.

With such medium to high-sensitive analog blocks in place, the normal power-up sequence of the PMIC would follow a particular order. The externally provided battery supply would first power up the analog blocks including LDO. We then make the system come out of reset (also called as Power-On Reset, viz., POR). Once this happens, the on-chip LDO would power up the digital logic and all the registers inside the digital logic would attain their default states, thus enabling the switching regulators inside analog portion of the chip. The digital logic registers can be programmed using standard protocols such as I2C, I3C, SPI, etc., in order to configure and enable/disable various features of the switching regulators.

Though the above mentioned blocks and sequence of operation are in general applicable to most of the PMICs, the number of LDOs, switching converters, etc., and their sequence timings might vary depending on the end application. The PMIC discussed here is targeted for consumer applications and it consists of couple of switching regulators, HFO and few LDOs as its key analog blocks. The key tests that were arrived at for verifying this PMIC can be categorized as:

· Basic Power Up and Power Down Sequence

· Tests for protection against various fault scenarios such as Over Voltage, Under Voltage, Short Circuit Protection, etc.,

· Dynamic Voltage Scaling

In order to run all the above functional tests and complete verification of the PMIC, it became imperative to adopt a Digital Mixed-Signal (DMS) verification approach using UVM testbench. This was required to save runtimes owing to the tight project schedule and the need to arrive at the test metrics that span across the PMIC’s capabilities as mandated by the customer within the available time. So a holistic verification approach that was devised and used for previous projects using UVM and behavioural real number model (RNM) using SystemVerilog was used for verifying this PMIC as discussed in [1].

Having said this, DMS based verification approach using RNM comes to a hard stop when the requirement arises to verify the analog behaviour such as supply and leakage current consumption of the chip, behaviour with respect to variation in supplies, temperature, etc. Verification of such behaviours are possible only by simulating the transistor level representation of the analog portion (assuming digital logic would not consume huge current), thus giving rise to the requirement of running Analog and Mixed-Signal (AMS) simulations. Models might suffice just for the HFO when simulating the dynamic supply and temperature variation, but for measuring the supply current consumption, the whole PMIC (barring digital) is required to be in SPICE abstraction.

Needless to say that this would end up in days/weeks of simulation time with traditional Spice simulators, since such simulators do not partition the design into multiple units but would solve the whole design as a single matrix. Although it ensures accuracy closer to silicon results, one cannot afford to wait for weeks to get the results in order to avoid the risk of catching issues such as leakage paths at a very later stage in the design and verification cycle. Thus a true Fast-spice simulation becomes the urgent need of the hour, keeping in mind the design complexity and the dense transistor population in a given area of the chip.

In this presentation, we would like to cover how we added the all-new Spectre FX Fast-spice simulator from Cadence to our top level flow, thus saving immense amount of simulation runtime. We would cover how we leveraged Spectre FX with its myriad of simulation modes to simulate the below test scenarios that required AMS simulations, and achieved adequate coverage in AMS with much improved TAT compared to Spectre X.

· Full Chip Power Up & Basic Sequence Check

· Dynamic Supply Variation

· Dynamic Temperature Variation

· Test Mode

Runtime comparison between Spectre X and Spectre FX, issues encountered during evaluation and adoption, and how we overcame them would be discussed. We would also cover couple of areas where we identified some scope of improvement for Spectre FX so that it adds value to AMS verification on top of its existing capabilities.

DRC spacing checks have become more complex as Companies move to smaller process nodes. These complexities are further complicated by designs containing multiple voltage domains, which have spacing requirements that are determined by the voltage level of the net.  Previous solutions to trigger the correct voltage-driven spacing checks required the Layout Designer to create marker shapes or text over the nets to identify voltage value.  This process is manual and has a high risk of human error.   If a marker was missed, or incorrectly placed on a net, it could result in missed real DRC errors and/or false DRC errors.

Cadence Design Systems understand the difficulties with this manual process and has released three VDR flows that help automate the process.   Skyworks has chosen to adopt the Schematic Driven VDR Flow.  In this flow the Circuit Designer annotates min and max voltage values on the schematic nets.  When the Layout Designer generates the layout from the schematic using Virtuoso XL, the voltage values are automatically propagated to the layout.  Once propagated, the Design Rule Driven editing recognizes the values and will apply the proper spacing values as the Layout Designer creates the layout.  Once the layout is completed, by the press of a button, the tool will add all the proper voltage marking or text layers needed by the DRC Verification tool. Thereby enabling the DRC to correctly identify the voltage and apply the correct spacing rule check.

This new flow reduces the risks of reliability problems. In addition, it minimizes the manual errors by simplifying the marking requirements and eliminates VDR related layout rework by enforcing the rules as the layout is created.

The complexities of analog designs at smaller geometries is driving an exponential growth in the number of simulations required for verification. For example, due to the rapidly increasing number of PVT corners.

Large Scale Cloud Simulation (LSCS) is the next generation Virtuoso ADE infrastructure for large simulation runs on premise and in the Cloud. It introduces a new architecture that overcomes previous performance limitations by optimizing netlisting and netlist storage, streamlining inter-process communication, and backgrounding CPU and resource intensive tasks. To manage the large volume of simulations, it enables new features such as resource estimation which helps users efficiently schedule simulation jobs, and advanced flow debugging and diagnostics.

We present the adoption of LSCS within NXP, showing how the analog simulator Mica was integrated into the flow with minimal changes, and present benchmarks to compare against the previous architecture.

Many complex requirements in memory IC design lead to pressure on turnaround time and design completion. This session will show how Samsung use ART routing for the complex memory IC design. You can see the chip assembly design mode for the memory IC design. The ART flow in Virtuoso allows user to have various constraints with no extra effort to build. ART has significant enhancements for Samsung technology, including support for the best routing channels and flow customization with a user-defined API. ART meets many complex manufacturing requirements on IC design. ART gives the best automated analog routing result using spine-style, matching, shielding and many other analog routing constraints. The final routed layouts are LVS correct and follows DRD with effective Virtuoso Technology file reference.

Interconnect modeling for inductance using stitching method has been challenging, especially in complex analog layouts, where the metal traces need to be partitioned, ports added to the traces, extracted for inductance to generate a model and then the model need to be manually stitched back into the circuit, for simulation analysis to identify the problem, which is seen in silicon measurement. Virtuoso-RF comes to rescue for this task and provides a faster and comprehensive solution for modeling of the inductance on complex metal traces in analog circuits. The paper will review the challenges that are seen for such modeling and how Virtuoso-RF has helped us to overcome the modeling challenge with some case studies.

In this paper, will discuss the challenges with the existing setup, then see the benefits of using the Virtuoso-RF tool using the EMX Solver engine for extracting the layouts, create the model and how the model can be seamlessly integrated into the Analog simulation environment.

In the world of ever changing semiconductor technology, time is of essence. We show an improvement to our AMS verification methodology, in particular, to create Configs-on-the-fly. Traditionally configurations are created to support one or more AMS tests, and our flow which was used during our internal PMIC development, generated approximately 45 configurations. Peer reviewing, tracking against the AMS testplan and maintenance (check-in and out of Design Manager) came at great cost of time with low productivity. Our flow was improved during the development of IOT low power power-management solutions, with the use of CONFIG SWEEP a global variable introduced for use with a maestro view, which is part of the Cadence Virtuoso Environment. Our solution, shows the use of a text based (ASCII) file, that is used to create  virtual configs, where the configuration is altered in memory. This works well with our flow, where we would like to utilise a single model based (verilogAMS) config view, which we define as our GOLDEN Config. Thereby in essence using a single configuration, thus improving the time spent reviewing, tracking and maintaining it. The flow is presently used in the development of another PMIC solution presently being developed by REE Harlow Design and Verification team. The flow has been successfully adopted by Renesas across multiple sites globally.

As each year passes, the “barrier” lines between the analog design and other types of design becomes more and more porous.  At Cadence, we have always promoted the close collaboration of our Virtuoso and Spectre platforms, and now more than ever the solid and trusted bonds between the platforms are providing the foundation on which we are building our latest technology.  In this presentation, we will give you a glimpse into both the technology of today and our bold ideas about tomorrow.  You will hear about the work we are doing with the cloud and machine learning that not only provide performance but also open up new doors of technology collaboration across Cadence tool suites.  You will learn how finfet design is revolutionizing electronics and how Cadence technology is on the forefront of delivering verified methodologies for solving the most difficult advanced node challenges. And finally learn about the latest expansions of the Spectre simulation platform that provide unparalleled performance and accuracy for the largest custom, RF, and mixed-signal designs.

The Virtuoso and Spectre platforms provide the right tools and the right answers, right now.

As each year passes, the “barrier” lines between the analog design and other types of design becomes more and more porous.  At Cadence, we have always promoted the close collaboration of our Virtuoso and Pegasus platforms, and now more than ever the solid and trusted bonds between the platforms are providing the foundation on which we are building our latest technology.  In this presentation, we will give you a glimpse into both the technology of today and our bold ideas about tomorrow.  You will hear about the work we are doing with the cloud and machine learning that not only provide performance but also open up new doors of technology collaboration across Cadence tool suites.  You will learn how finfet design is revolutionizing electronics and how Cadence technology is on the forefront of delivering verified methodologies for solving the most difficult advanced node challenges. And finally learn about the latest expansions of the Pegasus verification platform that provide unparalleled performance and accuracy for the largest custom, RF, and mixed-signal designs.

The Virtuoso and Pegasus platforms provide the right tools and the right answers, right now.

The prolonged “megadrought” in the US southwest (California, Arizona, and Nevada) has reached unprecedented levels with major reservoirs in the region nearly expended in 2023. To successfully plan future water use during these conditions, states require tools that predict how much water the snowpack will provide the following year, an estimate called snow water equivalent. NASA is currently developing a fleet of drone-based radar-radiometer sensors under its enhanced-metasurface (EMTS) radar program, that will continuously fly over the Sierra and Colorado mountains to provide water estimates. This talk discusses the development of these sensors, and particularly some of the simulation challenges in snow-sensing that were solved by Cadence’s spectre simulation.

Accessibility of pins in Standard Cells in development stage by running the SoC implementation router, as the std-cell layout development is done in custom environment and their abstracts are consumed at SoC implementation level, where issues in accessing pins of standard cells are discovered during Place and Route (P&R) flow. This is costlier in terms of efforts and time which can be overcome by using this tool during library development phase itself. There is need to ensure that standard cells are clean by construction for Pin accessibility during library development phase in Virtuoso.

Pin accessibility can be checked using varied and flexible standard cell placement topologies, utilisation, varied Top Metal Layer, by choosing various voltages, and variable critical net configurations to use double cut vias.

In this paper, we are discussing the methodology for pin accessibility check and integrated environment developed for quick use of SoC routing tool (Innovus) in custom environment (Virtuoso) to check pin accessibility in standard cells during library development stage itself. For creating SoC like scenario early in library development stage, we have developed different practical placement topologies of std-cells, considering different routing options to create congestion and using digital tool's technology LEF rules. The tool can report all routing statistics with DRC violation if any because of accessibility issue of standard cell pin. Corrections can be made after analysing the output reports.

The above integrated environment is called Pin Accessibility Checker (PAC). By deploying this integrated tool and methodology, all errors caught systematically. The solution is fast and comprehensive, cost of implementing the quality check is very less compared to the gains achieved. The method is used across all process technologies on all deliverable standard cell libraries. We have seen zero occurrences of the issue.

The amount of data generated in 2025 is estimated to be 181 zettabytes (181,000,000,000,000,000,000,000 bytes). To accommodate this, the size of data centers keeps expanding, putting different servers of the same data center several miles away from each other. Optical fibers are a necessity between servers and leveraging Silicon Photonics (SiPh) comes into play. Within its SiPh PDKs, Globalfoundries (GF) delivers innovative, unique, feature-rich solutions to solve some of the biggest challenges facing data centers today.  

Parameterized Cells (Pcells) are a key component of our PDKs. “Best in class” automated validation strategy was developed over the years which allows for a high level of quality for an ever-growing list of supported PDKs. The well-known, forever challenge of Pcells validation is the daunting number of possible configurations of parameters to generate distinct layouts. To focus our efforts, our automation algorithms have various level of complexity but in the end, it’s about picking parameters values and placing them on a layout to run our battery of tests.

SiPh brings a new, exciting challenge to Pcell validation. Some photonics Pcells have an atypical usage model.  They are fluid pcells which have few parameters in the CDF, instead providing a wide range of flexibility through graphical editing.  Our legacy validation strategy did not exercise this flexibility and covered only a non-representative sample.  A new strategy is needed to exercise these pcells.

To solve this problem, we worked in collaboration with Cadence on some SKILL utilities which allows the automated generation of both deterministic and random fluid shapes to fully put our photonics pcells to the test. Through this partnership, the following hurdles were encountered:

Should the generation of photonics pcells (like waveguides) be deterministic, random or both?

How can the problem of moving a fluid pcell in any number of degrees of freedom be captured in SKILL equations for automation? How to further ensure these equations reflect real design configurations?

Should this utility be limited to a script used for GlobalFoundries internal QA team, or extended to a designer utility with a proper GUI?

This collaborative work will reveal other opportunities in Silicon photonics PDK automation with SKILL and we are eager to exchange with the audience on this subject.

High-voltage design circuits are common in SoC design applications. They have their own challenges associated with the whole flow and methodology implementation. One important aspect is maintaining DRC rules based on delta voltage between different nets, which is a very tedious process when you have hundreds of nets running in the design. The traditional method involves schematic annotations to be followed by the layout designer and replicated in layout design using labels. This is not only very time consuming, but also error-prone method resulting in sometimes missing labels. 

This drives the need of some automated utilities, which not only capture the dataset, but also can easily be exchanged between schematic and layout views. VDR simulation-driven label creation allows capturing of accurate voltage information for each net based on simulation data and automatically creating labels on layout side. This also helps other automated and interactive tools in the Virtuoso environment to consume this information and follow a correct-by-construction approach for layout development. Simulation-driven VDR flow helped achieve 6,000 hierarchical net labeling in approximately 30 minutes, a good productivity gain as the manual approach would take around four to five days.

As a design evolves from architecture through logical and physical implementation, accurate PPA visibility at each design stage is required to make tradeoffs that yield the most PPA-optimal design. This presentation discusses how Celestial.ai, a Machine Learning accelerator startup, met their design PPA goals using a Cadence full-flow composed of Stratus High-Level Synthesis, Genus iSpatial, Genus Logic synthesis and Innovus physical implementation that features PPA accuracy and coherence at each design stage.

As the number of instances and complexity increase at each release of a new GPU and also when moving to smaller nodes such as N5, and N3, it is essential that the overall implementation TAT stay steady or even decrease to ease engineers’ tasks.

This paper will present the work that has been done to decrease the overall implementation TAT while maintaining good Power, Performance, and Area (PPA) on a recent high-end ARM GPU Core. In the paper, we will compare the ARM GPU standard flow to a flow tuned with new features, available starting at 22.1X. These new features are place_opt_design V2, clock_opt_design, and route_opt_design. The paper will then present and show how we have used those features to get the best recipe to reduce the overall TAT, while the PPA stay similar.

This recipe which enables better TAT is now fully adopted by ARM GPU for the latest Cores and is under advanced investigation across some ARM groups, like CPU Cambridge and Sophia.

Currently, power is one of the most important factors in IC designs. Having a low power and power efficient design is of utmost priority to most designers. To compute this power accurately, designers tend to wait for the RTL to be synthesized and be implemented in place and route. This is where Xreplay flow comes to the rescue whereby it helps the designer to estimate this power at a much earlier stage and also helps the tool generate a more power-efficient design by running the netlist level simulation automatically without manual intervention. This new technology feature introduced in Genus & Innovus 22 as part of DDIv22.1 version takes in an RTL stimulus along with Joules and Xcellium to not only help generate power numbers that correlate to the power post place and route but also help Genus & innovus generate more power efficient netlists without performance sacrifice.

The flow first takes in the RTL along with a stimulus generated by simulating the RTL, to synthesize a more power-efficient netlist whilst generating power numbers in correlation to Innovus numbers. The flow then takes the netlist generated through Genus, into Innovus along with the stimulus file to run place and route. Power numbers are generated after each stage in both synthesis and place & route. This flow not only optimizes the design in-terms of power, but also help eliminate the separate standalone runs. Whether it be standalone simulations you run on the gate-level netlist or place & route netlist, or it be standalone Joules run to generate the power numbers. This flow helps you achieve all of that in one single automated fashion with full 100% annotation of toggle activities. These numbers have been verified and correlated with the standalone runs.

We introduce Mixed row flow to get more performance and area gain on specific range by combining two libraries together.

The contribution of mixed row flow is to improve PPA without development of new library for specific application.

The technical challenges of mixed row flow such as aligning with rules between two different libraries and decision on row ratio are addressed for better PPA sweet-spot of mixed row flow.

To deal with these challenges, we modified several design rules and used hybrid power rail to solve the broken rules.

We enable a new design method to resolve the placement constraints through cell swapping over rows.

It is also shown that a proper row ratio can improve area & performance Combination of cells varies depending on target frequency.

In this works, we demonstrate 4.1% area gain and 9.1% performance gain in high performance design and 6.1% area gain over library for high performance and 2% area overhead over library for high density in high density design.

Advanced process nodes and chiplet-based designs are pursuing increased capability with improvements in power, performance, and area.  This is driving the need for enhanced visibility within devices for many effects: design sensitivities, material variability, latent defects, accelerated silicon aging, and the impact of software on hardware. New methods are needed to ensure the design meets usage requirements. From characterization and qualification, through test, and during lifetime operation in the field, a predictive approach is needed. This presentation will highlight a new approach by proteanTecs for health and performance monitoring of advanced electronics from design to the field, using deep data analytics. By combining on-chip agents (monitoring IPs) with ML-driven analytics, manufacturers and service providers can roll out devices with mega-functionality, at scale - safely, reliably and cost effectively. By fusing measurements from the agents, design simulations, and customer data, the company provides newfound insights for mission-critical applications, such as datacenter, mobile and automotive.We will review the Cadence implementation workflow for integrating proteanTecs technology, in use today at leading semiconductor companies.  Leveraging the capabilities of Innovus and Spectre, we have simplified the implementation process and improved device learning.  As a provider of both soft and hard IPs that are inserted into an existing functional design, proteanTecs minimizes the effort by the user through the use of Cadence tools.

With the rapidly raising number of computing and peripheral building blocks in modern System on Chip (SoC) development easily being in the 100s, the interconnect between these blocks can become the long pole for timing analysis and significantly contributes to power consumption. Networks-on-Chips (NoCs) have emerged as the key solution for on-chip communication and have seen a rapid rise in protocol complexity for coherent and non-coherent designs, and flows for automated RTL generation from high-level NoC topology descriptions have emerged. With the transport delay being increasingly dominated by RC wiring delay, changes in the NoC topology caused by difficulties in timing closure during the Place and Route (P&R) phase can add significant project delays. This presentation will outline a flow and methodology that uses earlier, abstracted technology information to efficiently guide the development of NoCs using .lef/.def based import of floorplan information to inform NoC-topology development and export constraint and  placement information as guidance to Genus/Innovus-based digital implementation flows to avoid late surprises in timing closure.

DOJO is designed to be scalable computer to train the ML networks that run on the Tesla’s FSD computer in Tesla Vehicles. D1 chip is the ML training processor in the DOJO exa-scale computer system. D1 is an array processor that has 354 compute processors and 440MB of SRAM, 9TB/s of off chip bandwidth per edge, with 2-dimensional network on chip high bandwidth that connects the compute processors. In this presentation we would like to cover the physical design methodologies used for first pass silicon success. We cover the construction methodologies used starting from the processor design, integrating the 2D network fabric, channel less floor planning, cloning of the processors aware of clocking and static timing analysis challenges, electrical analysis and physical verification methodology used in achieving the first pass success and how cadence tools were deployed.  Further we cover the tools and methodologies used to scale the D1 processor into a tile on wafer level integration and tools used for the convergence of the tile for scaling the compute and IO.

Market demands are as fierce as ever, meeting schedules is critical, and having design flow flexibility for last minute design bugs fixes and specification changes is a necessity to remain competitive. Leveraging maximum automation in this area is a key advantage. In our paper, we will describe how CFM ECO can be used to help automate the ECO process, share our experiences and best practices in how to setup a functional ECO methodology for both pre and post-mask flows. We will describe how a solid formal verification equivalency checking process for independent verification is fundamental, and how it is leveraged for ECO automation. Our goal is to automate the process as much as possible. We will describe how CFM ECO has helped in achieving this goal, share our experiences, and describe the end benefits of automating functional ECOs vs. manual ECO efforts.

Modern chip design requires multiple project tradeoffs at different points in the design cycle, which can impact final power, performance, and area (PPA). As the design matures, the costs of re-opening a block for another round of implementation grows prohibitively expensive, both from a schedule and design impact perspectives. Engineering changes orders (ECOs) are functional short circuits to a full implementation pass that can address targeted fixes in an order of magnitude less time. This paper summarizes the latest features and flows available for Conformal ECO users to automate functional logic ECOs in their flow.

Cadence engineers will share the latest features and technical Conformal ECO best practices from working with many customers across different design styles on recent designs . Topics include: ECO recipes for optimal patch sizes, extended mapping analysis and key point mapping generation, using RTL-Diff information to understand the scope of the RTL changes and to improve patch sizes, ECO partitioning for improved debug, introducing cut points to limit ECO scope and improve results, and other R&D recommend techniques. Join us to hear how Conformal ECO will help you tapeout functionally correct designs on time.

As design teams implement and signoff the most challenging designs across a wide range of foundry process nodes, the Cadence Digital full flow is continually improving to enable the best power and performance results for ever larger and complex system on chips (SoC). During this session, Yufeng Luo, VP of R&D, will discuss new digital full flow technology such as the latest 2nm features, 3D-IC multi-die partitioning, high capacity signoff design closure and Cerebrus AI driven design optimization and data analytics. Join this session for a deepdive into the latest Cadence R&D digital full flow innovation.

Driven by requirements to deliver increased performance and lower power for specific workloads, designers increasingly turn to architectures composed of processors plus hardware accelerators. The Tensilica and Stratus product teams within Cadence are delivering an automated solution for developing and analyzing the performance of systems composed of Xtensa processors and Hardware Accelerators. The solution delivers early performance, power, and area (PPA) measurements to enable more accurate HW/SW partitioning decisions. The solution also automates system configuration and the production of optimized RTL. This presentation will discuss the details of the integrated solution and present experimental data on PPA and schedule.

In the advance nodes such as 5nm or below delays are becoming small, data paths are getting longer, and any glitch propagation can cause dynamic & internal power jump and functional issue like error propagation. With the complex cells designed for data path components, more and more glitch power occurrence happening in the design at advanced nodes.

As of now not many implementation tools can do glitch analysis and reduction properly, but with proper debug methodology and applying correct settings to synthesis we can reduce the glitch effect.

As a case study, the session will outline the techniques used to minimize glitch power in implementation with delay-based simulation calculation. This session will demonstrate the Joules xReplay technology, which leverages the Xcelium simulation engine to generate cycle accurate SDF based activity for glitch analysis. Joules xReplay feature can provide detailed guidance on the source of glitch power in the design. The information generated from Joules xReplay helped us to guide the Genus tool in selecting better data paths structure for glitch reduction. With these techniques, ~20%-30% glitch power improvement observed for the given use-case.

The goal of this session is to demonstrate how attendees can use Genus/Joules xReplay effectively for glitch analysis & power reduction in complex data path designs at advanced nodes.

As advanced electronic communications systems encounter a greater need for heterogeneous integration of mixed signal technology, a bridge tool between (1) RF simulation and design software and (2) general electronic design automation tools is becoming increasingly necessary. Cadence AWR Microwave Office is a powerful tool for simulating, designing, and developing RF and microwave components and circuits. However, the tool is limited when trying to create larger RF boards and systems as project management and layout complexity increases dramatically. Conversely, Cadence Allegro is a powerful electronic design automation and board layout tool, but does not have native capabilities for microwave simulation.

At Systems & Processes Engineering Corporation, we are designing our next-generation RF signal processors and transceivers by using the Cadence Unified Library, along with AWR Microwave Office and Allegro. We present our work toward a general RF-to-PCB workflow by showing how RF parts and modules that have been previously and are currently being designed by us using Microwave Office can now be more efficiently integrated into board designs that are laid out using Allegro, creating smoother system development and leveraging the individual strengths of Microwave Office and Allegro to create powerful integrated RF/mixed signal packages.

OLogic will go through a real customer scenario where the client was having EMI issues during compliance testing. The customer came to OLogic to identify the cause of these EMI issues and provide a solution to allow for class A/B compliance. OLogic will go through their process and work flow using Sigrity for post layout analysis, Sigrity model extraction, and S parameter and EMI analysis. This flow is used to help them quickly and accurately identify potential problems areas and then converge on solutions to fix and validate the issue for the customer.  Along with reviewing existing work flows we will discuss some of the work being done inside our organization to further optimize our design flows and leverage simulation at all levels of design to help with future construction of PCB design projects.

Eight -year-old Zeke Wheeler posed a casual question about how he could call the astronauts on the International Space Station (ISS). This resulted in his Federal Communications System (FCC) radio station license and a three-year epic adventure to contact the ISS using circuit boards and antennas he researched, designed, and built with his dad. This project involved as many obstacles as successes and provided invaluable science/technology/engineering/mahematics (STEM) learning along the way. 

This presentation will cover 3D EM simulations of a dual band helical antenna with Cadence Clarity 3D Solver, as well as circuit board designs of a satellite’s tracking motor controller, diplexer, bias tee, and low noise amplifier (LNA), which were designed using Cadence AWR Microwave Office circuit design software. 

This presentation will cover 3D EM simulations of a dual band helical antenna with Cadence Clarity 3D as well as circuit board designs of a satellites tracking motor controller, diplexer, bias tee, and low noise amplifier that were designed using Cadence/AWR Microwave Office.

This session overviews Cadence’s new electronics cooling and digital twin solutions acquired from Future Facilities. Celsius EC Solver electronics cooling software and digital twin solutions.

The Celsius EC Solver was designed specifically to enable electronic system designers to accurately address today’s most challenging thermal/electronics cooling management issues. The software was leveraged internally by the Cadence Palladium Emulation R&D team to develop a second-generation hybrid solution combining both liquid cooling and air cooling that is much easier and more cost-effective to manufacture than liquid cooling alone, while still meeting performance requirements. 

Specific to data center management (design, implementation, and operation), data centers are a major consumer of energy/greenhouse emissions worldwide.  The Future Facilities 6Sigma Digital Twin solution, now Cadence Digital Twin System, addresses sustainability metrics (green house/emissions, power usage/thermal output, etc.) for customers in the hyperscalers, banking and medical domains, to name a few.  

Select customer case studies illustrating these electronics cooling and digital twin solutions, including Cadence examples, will be shared.

While working with a host of customers this last year we continue to hear “simulation-measurement is a bit of a black art”, or “no, we don’t really close the loop on our high-speed design process”, or maybe “we thought our measurements were really good, no we have not questioned that…”, etc.

Top-gun teams from Cadence and Wild River Technology (WRT) gathered to address fundamental problems of practical electromagnetics using Cadence Clarity and the WRT Channel Modeling Signal Integrity tool, the CMP-50.   Topics covered will be, the influence of measurements techniques and fabrication on the physical side and boundary conditions and material identification for simulations. How do you localize the correspondence, do you need de-embedding?   A common problem with VNA measurements is additionally addressed.  We will conclude with guidelines to improve physical measurements and recommendations to ensure correlated Clarity electromagnetic simulations.   This is a hard-hitting practical discussion relevant to all folks using a host of EDA tools and test hardware.

Imagine a world where you can be present in every moment you want, unrestricted by distance? Technology has long helped us feel a sense of presence, but its capabilities are currently limited. In the future, Mixed Reality (MR) and Virtual Reality (VR) will elevate human connection to new, unprecedented levels, allowing the world to come together authentically and meaningfully, regardless of physical boundaries. MR and VR play a pivotal role in helping people to feel present and have emerged as new media that is truly people centric. In the past few years, several emerging MR/VR capable hardware devices have gained great popularity in both consumer and industrial markets, such as the Meta Quest 2/Pro and Microsoft HoloLens. Usually, the electrical design of these devices consists of a series of interconnected Rigid-Flex PCBs (RFPC) that contain both rigid and flexible substrates laminated together on the same board, satisfying tight form factors and weight constraints. In particular, the system power delivery design from battery to many different voltage regulators spread across multiple RFPCs is very critical to ensure the full functionality of the entire device. However, simulation and optimization of the DC resistance and DC IRdrop across such a multi-board system is a challenging and time-consuming task. Traditionally, each board can only be extracted individually, and resulting resistance networks must be manually stitched together in a spice-like circuit simulator. In this paper, we introduce a unified DC IRdrop simulation flow targeting a multi-board system with multi-zone/rigid-flex type of designs. Some of the unique challenges of multi-zone/rigid-flex designs include multiple stackups for different zones and components being placed on top/bottom layers of each individual zone. For the newly proposed multi-board flow, we leverage Cadence PowerDC to seamlessly consider components that are placed on top/bottom layers of each individual zone as potential connection ports to the neighboring RFPC. By building a block-based system in PowerDC, we are able to accurately simulate the board-to-board DC IRdrop across the system PDN stack, pinpoint and mitigate higher current routing areas and hot spots. The implemented flow showed great simulation-to-hardware correlations, and it was validated via real measurements of the DC path resistances from battery connector to various system regulators located at different boards.

The complexity of the power delivery network (PDN) can make it difficult to visualize the delivery of power from all power sources to all sinks inside a PCB power integrity tool. This paper examines the Cadence® Allegro® PowerTree™ technology, which provides the big-picture vision of power delivery, and demonstrates achieving signoff with accurate DC and AC simulations using the PowerTree flow. It also presents lab measurements correlating simulation results for MR/VR PDN designs.

The detailed art of MMIC design often involves evaluating and optimizing a design using different assumptions or operating conditions.  The switch lists feature in Microwave Office is a powerful method to simplify this process while maintaining a well-organized project.  Knowledge of this feature seems to be limited in the MMIC design community; therefore, this talk will introduce switch lists and provide examples showing how they can be useful during the MMIC design and analysis process.

Validating PDKs signoff decks such as DRC or DFM is critical because they are the gate keeper for manufacturability. However, these decks are difficult to validate as foundries do not have access to enough proprietary customer design data, and for this reason, cumbersome manual layout creation and verification is often used. In the pursuit of automation and less error-prone workflows, the Virtuoso® Application Library Environment (VALE) by Cadence that allows the integration of multiple modules under one configurable interface was used in this work to create electrically-aware validation test cases and enable automatic validation. We applied this flow to the GlobalFoundries 22nm DFM DRC+ and DFM Pattern Optimization (DFMPOP) deck which enables a powerful tool to automatically detect and fix DFM violations and meet DFM compliance. The scope of this work includes pattern enumeration to generate test cases and then this was coupled to pattern matching and fixing modules all within GlobalFoundries 22nm PDK deck. We discuss the technical setup procedure, and the solutions VALE provides. We further discuss potential promising applications in PDK development and testing, along with potential machine learning flows for pattern generation and testing within required design signoff for manufacturing such as DRC and DRC+.

In-design signoff verification at the early stages of layout development is essential to achieving signoff clean layout. It is critical to catch DRC violations and predict metal fill impact early in the design process for faster full flow TAT and shorten the design cycle time to boost productivity. Learn how in-design signoff verification on advanced process nodes like Samsung 3nm Gate All Around and above provide a signoff-quality on-demand or post-edit DRC verification and fill insertion on either the entire layout or partial layout depending on layer visibility or changed area.

In this presentation, we will discuss our evaluation of Cadence Certus for our 7nm SoC and provide a contrast of using Certus in our flow versus our current methodology. We will discuss the turnaround time benefits and also timing and power optimization QoR at a full chip level.

In ths presentation, we will discuss timing and most importantly power optimzation challenges for advanced nodes designs. We will discuss evaluation of Cadence Certus for our 16nm design and share the benefits of the tool for our production flow moving foward.

Embedded memories comprise a large percentage of silicon area on most of the chips consequently being a major contributor towards chip performance and power consumption. Hence, Library characterization plays a vital role in digital design flow. The electrical models generated need to be highly accurate. The electrical views generated is utilized in logic synthesis, design optimization and sign-off verification.  The major task is for the electrical views generated from Memory instance/compiler characterization to be in sync with the design architectures and changes. Memory characterization flow is very complex and requires characterization of hundreds of arcs, on tens of slew-load combinations, for tens of memory design features and covering variety of char views and design complexity in advance nodes add more complexity to the job.

The focus of the ST TDP MEM IP Team is to develop diverse platforms for Automotive, Imaging and secure MCU with specific architectures. These specific designs in various domains demand a wide requirement for lots of Manual and characterization methodologies. Also, characterization becomes a challenge when the standard IPs are taken from external vendors where the design will be a black box. Characterizing the dotlibs automatically in such scenarios is the need to the hour. The typical methodology used in characterization, from measuring different arcs with respect to number of slew load combinations for a wide range of designs and functionalities and assembling it as a library, framing it in different views is a very tedious task which could lead to manual errors and complexity in work, hence creating an opportunity for Liberate MX flow to generate this data.

STMicroelectronics and Cadence have worked together to establish characterization flow based on Liberate MX in latest ST eNVM technology node, CMOS P18. It is seamless to generate memory liberty files for any supported instance and PVT corner supported by memory compiler.  Liberate MX has been modelled to capture arcs related to a lot of complex features that take huge efforts from the designer and create the characterization setup. 3rd party user need not to know complete arc wise critical path designs to capture the arc as LMX automatically understands the arc critical paths. The flow provides a facility to retrieve the data regarding different arcs from the existing libraries and write a template file further reducing efforts from the designer. Libraries are generated in different formats like NLDM, CCS and LVF. The generated libraries can also be verified using the Validation flow. This paper demonstrates how ST has leveraged Liberate MX capabilities to generate signoff quality libraries with reasonable turn-around-time.

Lightmatter needed an effective, efficient development environment to ensure the verification team can keep pace with the rest of the organization. The need of the hour was to improve iteration time as the designs were taking almost an hour to re-elaborate.  Any minor change required re-elaboration of the complete environment. Most re-elaboration iterations by the verification team were because of improvements and development in the verification environment, not the DUT. Nothing improves engineer focus, happiness and productivity like short iteration times.

Deploying MSIE ”Multi Snapshot Incremental Elaboration” gave us an order of magnitude improvement for these changes because it automatically detects that only the test bench has changed and only re-elaborates that. This paper covers the steps needed to take to deploy, the changes made to our environment and the tool switches that allowed us to understand our dependencies.

Abstract: Firmware development and validation is a critical aspect of the product development cycle. Growing complexity of firmware along with its hardware counterpart has put tremendous pressure on the engineering teams to explore effectively and efficient ways to validate the firmware. Firmware validation is often gated by the hardware availability and slow simulator speed. Time-To-Market being the critical factor, waiting for the actual silicon to arrive to begin testing the firmware is simply not an option . Traditional FPGAs offer real-time speeds but the bring up duration eats up months for complex projects and debug remains a nightmare and resource intensive. We wanted a strategic trade-off solution addressing both HW and SW Engineer’s needs in terms of bring-up time and debug. The “Dynamic-Duo” PalladiumZ2 and ProtiumX2 “Congruency-flow” solution from cadence addresses these challenges in a much efficient way and we will demonstrate how we achieved the best of both platforms in ADI’s complex products.

Unified Congruency flow (PalladiumZ2 and PrtoiumX2)

This paper focuses on the Cadence Dynamic Duo’s congruent flow and its capabilities to enable pre-silicon debug and pre-silicon software validation for the complex designs. The major advantage of this Dynamic Duo is its unified congruency flow . Palladium Z2 and Protium X2 platforms have similar compile tools to elaborate and generate the design netlist compatible for both platforms. As shown in figure 1, for ICE flow, the tools used for sourcing, analyzing, generating netlist and the backend compiler are all similar – vavlog, vaelab and xeCompile. The netlist generated using vaelab stage can be used by both Palladium compile flow as well as Protium compile flow, which eliminates recompiling and generation of netlist again. Additional steps in Protium compile flow involves Place and Route which generates the bitstream to be downloaded on the target FPGAs.

The “unified congruency” flow has been enabled for full fledged System validation of Transceiver designs by

• Effective Firmware infrastructure development using Physical JTAG and Virtual UART solutions

• Successful integration of Denali MMP Models 

• Easy bring up and Migration from Palladium to Protium

• Ease of debug using IDA (Palladium) and DCC card/chiscope (Protium)

Migrating the design from Palladium Z2 to Protium X2

• Palladium Z2 and Protium X2 both support the ICE (IN-Circuit Emulation) and IXCOM flow. 

• The tools used, xeCompile and IXCOM, are common for both platforms, with Vivado being an additional tool in Protium for FPGA bitstream generation.

• This unified compile flow helps easy migration of design between these platforms.

Arm SystemReady is a compliance certification program. It relies on architecture specifications such to enable hardware/software portability, so that generic and off-the-shelf operating systems, hypervisors and firmware can work out-of-the-box on Arm-based devices. For silicon vendors, it means reduced software development costs and faster time-to-market. For device manufacturers and developers, it means a streamlined software deployment model and greater market scalability.

This session focuses on SystemReady Pre-Silicon. I.e. designing and testing for architecture compliance prior to tape-out, in a well-defined and low-risk path, so as to prevent costly re-spins and software workarounds.

This session provides an overview of the BSA/SBSA specifications, the silicon journey, and common compliance issues. It provides details of the methodology to test for pre-silicon compliance developed in collaboration with Cadence for simulation and emulation. It focuses on bare-metal testing (for faster debug cycles early in the design cycle), testing on UEFI (for minimal integration and porting), and Exerciser tests (PCIe AVIP, a controllable PCIe endpoint, for a complete architecture compliance coverage).

Lightelligence’s next-generation Photonic Computing Engine incorporates an integrated photonic Matrix Multiplication engine and corresponding electronics delivered in a single multi-die 3D system in package (SIP). This design allows the engine to deliver unprecedented performance in both Artificial Intelligence (AI) and non-AI applications. The SIP design includes an electronic integrated circuit (EIC) containing digital processing elements, analog circuits, and high speed IOs, and a separate photonic integrated circuit (PIC) containing couplers, modulators, waveguides and photodiodes, all of which present new design and verification challenges. While the design process is a daunting task, the novelty here is to leverage the Cadence Integrity 3D-IC platform and its seamless co-design methodology. In addition, the use of Universal Verification Methodology (UVM)-based validation and the Palladium emulation environment accelerate the verification and hardware/software co-design process.

The Integrity 3D-IC tool reduces the complexity, improves the robustness, and streamlines the multi-die physical design flow. Consequently, the high performance PIC and companion EIC can be designed holistically, efficiently and meeting target specifications. It not only ensures accurate stacking of µBumps and through-silicon-vias (TSVs), but also shortens the design cycle. The integrity 3D-IC platform, Innovus, Voltus, Pegasus and other powerful EDA point tools work seamlessly to optimize implementation, power integrity, and system level LVS signoff.

Furthermore, the complex heterogeneous optical architecture and the underlying multi-die system leads to a considerable verification challenge. It is difficult to assure the quality of the product when only using traditional approaches and simulation methodologies. This paper also presents an efficient methodology to improve quality and reduce overall verification time for heterogeneous photonic and electronic designs. Lastly, an emulation platform based on Palladium is developed to qualify and expedite the project, exercise the shift-left methodology and pull in tape out time for both silicon and photonic designs.

User-Defined Nets (UDNs) are specific kind of net introduced as a System Verilog construct (called “Nettype”) starting with 2012 LRM. Electrical Equivalent net (“EEnet”) uses UDN as the basis to effectively model the actual level of impedance-dependent interaction occurring between modules and implementation of that functionality. The EEnet model resolves the voltage, current, and source resistance driven from the testbench drivers onto the EEnet.

Analog/Digital Mixed Signal (AMS/DMS) simulations, which use EEnets for the device pins with multiple drivers, have gained popularity due to its accuracy and performance. Although build and run times may increase with EEnet usage compared with non-EEnet models, the performance will still be several orders of magnitude faster than simulation using an analog engine.

These EEnet models have found applications for basic and the most commonly used components. These models will help a) speed up model generation for design verification; b) provide a template for more accurate model creation; and c) train new users to gain first-hand experience of EEnet modeling. As with any modeling, a solid method is needed to debug or profile EEnet related performance issue.

In this paper, we show two libraries Cadence is going to release along with Xcelium to address EEnet model generation:  EEnet - This is the component library (systemVerilog, symbol views); EEnetTest - This library contains several example test cases (schematic, config, maestro views). The examples provided also illustrate the attribute based EEnet current probing technology for both command line and Virtuoso use models. This paper presents an Analog-on-top case study using Electrical Equivalent net (“EEnet”) models. A newly developed EEnet profiling technology in Xcelium is used to help debug performance bottleneck.

As semiconductor products have become increasingly complex in recent years, the time spent on debugging in the verification phase has also steadily increased. Therefore, one of the major challenges is how to improve debug turnaround time. A typical approach to improving debug turnaround time is to automate repetitive debugging tasks. Examples of repetitive debugging tasks include checking several signals and confirming their behavior, tracing signal drivers, adding extra messages, and so on.

The Verisium Debug Python API provides a solution to these challenges. Simulation-related information such as waveforms, design data, and log messages can be read and processed in Python. This information can be used to automate manual work or complex debug using Python scripts that call custom applications (Custom Apps). Users can create their own Custom Apps to reduce debug turnaround time.

There are two approaches to creating Custom Apps. The first approach is to automate repetitive tasks; debug information can be viewed without requiring the GUI to be launched with so-called “data mining” applications. For example, reporting all the glitches in a waveform database or extracting arbitrary signal values which matches specified condition. The second approach is to improve debugging efficiency in GUI operations. This goes beyond the limits of a generic GUI. For example, multiple GUI operations can be executed in succession, custom buttons can be placed on the GUI to implement arbitrary functions, and debug time changes and signal selection states can be hooked into callback functions.

This presentation will show several examples of how the Verisium Debug Python API can be used to improve debugging efficiency. It will also show how to use the Python API and how to search for useful APIs.

The RISC-V instruction set architecture (ISA) open standard has accelerating momentum in the semiconductor community.  Adopters include both traditional semiconductor companies and vertically integrated systems companies building their own SoCs.  This momentum is due to the open nature of the ISA, enabling users to build domain specific processors that can help to differentiate SoCs and end products.  This flexibility is a double-edged sword.  Unlike traditional processor IP, custom instructions are routinely added to RISC-V processors.  This means that the ecosystem – both hardware and software tools – needs to be adaptable to these custom instructions. 

Two issues that need to be addressed for RISC-V SoC success, processor verification and software porting, development and bring up, are key areas of the RISC-V ecosystem. Software simulation coupled with hardware emulation addresses both these areas, providing a methodology for software development, whether porting software or new development, and for processor verification through hardware-software co-verification. 

This paper reports on the use of Open Virtual Platforms (OVP) Fast Processor Models for this hybrid simulation-emulation technique.  Custom instructions and other custom features of RISC-V processors are discussed, and the modeling architecture and development methodology for achieving high quality, high performance (~500 million instructions per second) processor models is presented.  The processor models are integrated with the Helium SystemC simulator, enabling the hybrid simulation-emulation usage with Palladium.  When used in this hybrid methodology, booting Linux in the fast processor model coupled to peripheral execution to the emulator, performance improvements of over 100x can be achieved versus standalone emulation. 

While this flow has been proved out using Palladium, the congruence with Protium means that FPGA prototyping could also be used in this hybrid mode. 

This paper features a customer use case involving the development of a SoC for AI/ML with a large number (many 10s) of RISC-V cores, highlighting how hybrid simulation-emulation is critical to the success of this RISC-V based SoC.

There are a lot of things that can be challenging when we are talking about SoC hardware and software verification. Engineers are torn between high requirements to achieve verification results fast and the complexity of the system. This paper gives an overview of the flow that is followed in the multi-platform verification of the Ethernet Subsystem. There is a concept of a verification plan with a list of important segments of Ethernet SoC verification. Each segment is verified on the most suitable platform. Our success story tells about Ethernet features tested in formal verification, RTL and GLS simulation, emulation platform and FPGA. The re-usability of testbench parts over different platforms is highly promoted during the whole process. The accomplished results demonstrate that this flow can be used as a roadmap for other teams that could have some dilemmas in making decisions in the verification strategy.

Modern test equipment uses both FPGAs and ASICs verified to stringent quality requirements.  Functional verification, CDC analysis, and lint analysis each contribute to that high level of verification. Traditionally, each has been executed independently but with integrated engineering teams and increasing time to market, there is a desire to unify these three.  Teradyne recently upgraded their existing tools to Jasper CDC and Superlint Apps so that FPGA and ASIC teams can operate the same flows and to create a path to unifying the results with functional verification using Verisium Manager. This paper will focus on how Jasper CDC and Superlint are used in both ASIC and FPGA flows as well as how the results can be integrated in vManager.