CadenceLIVE India – OnDemand
Computational Fluid Dynamics
On the Requirement of Interior Artificial Boundary Surfaces as Part of Pointwise Unstructured Grids
Jyothi Kumar Puttam, CSIR-NAL
Shikhar Jaiswal A, CSIR-NAL
Madhu Babu K., CSIR-NAL
Arshad Shameem C, CSIR-NAL
Sharanappa V Sajjan, CSIR-NAL
Venkatesh T N, CSIR-NAL
CFD-1
Development of a Framework using Pointwise Glyph Scripts for Automatic Mesh Generation from Surface Mesh for Configuration Changes in Aircraft Design
Shikhar Jaiswal A, CSIR-NAL
Madhu Babu K., CSIR-NAL
Jyothi Kumar Puttam, CSIR-NAL
Arshad Shameem C, CSIR-NAL
CFD-2
Custom and Analog Design: Implementation
Expediting Routing and DRC Signoff by Partitioning Large Layouts using Virtuoso CLE
Deepak Agarwal, AMD
Apparao Yadalapurapu, AMD
Naga Rajender Vijapur, AMD
Gautam Kumar, Cadence
Yuan-Kai Pei, Cadence
Vishesh Kumar, Cadence
CADI-1
Advanced IP Compiler Based on Relative Placement Methodology
Hariprasath Baskaran, Intel
CADI-2
Methodology to Reduce TAT by Delivering High Quality Physical Views for Migrated IP
Abhik Gupta, Intel
Ashma Malik, Intel
CADI-3
Virtuoso Integrated Solution for Analyzing the Impact of Top-Level Parasitics (R&C) in Block-Level Simulations
Veerabhadresh Hugar, Texas Instruments
Shanmuga Narayanan, Texas Instruments
CADI-4
Comparison between Manual vs Automated Layout Methodology for Mixed-Signal ICs Using APR Flow
Akshay K Siddamal, Intel
Manivannan M, Intel
Kevin Park, Intel
CADI-5
EM-Aware Interactive Routing Methodology of Analog Layouts Using Virtuoso SDR
Sathish Rao, Marvell
Dhanesh Kumar Pragasam, Marvell
Sandeep Torgal, Marvell
CADI-6
Accurate and Fast EM Solution for LC-VCO Design, Using Virtuoso RF EMX Flow
Rajeev Singh, STMicroelectronics
Kapil Kumar Tyagi, STMicroelectronics
Prayes Jain, Cadence
Madan Rachaprolu, Cadence
Vishesh Kumar, Cadence
CADI-7
Productivity Expedience of Custom Layout Using Virtuoso CLE with Feedback System
Krishna Basidoni, Marvell
Akshay Murade, Marvell
Vinay AB, Marvell
Sriram Bishnoi, Cadence
CADI-8
Custom and Analog Design: Verification
Next Level of LVF Characterization Using Liberate MX
Parmanand Singh, Arm
Dakshesh Malaviya, Arm
CADV-1
Methodology for Runtime Optimization of Analog Mixed-Signal Simulations
Aswin R, Texas Instruments
Nilesh Upadhye, Texas Instruments
CADV-10
An Efficient Way to do an IP Assessment Based on the New PDK Release
Neha Raj, GlobalFoundries
Jayanta Lahiri, Global Foundries
CADV-2
Extending RTL- SPICE Simulations to UPF Based Verification for Low-Power Architecture in the SoC
Nitin Pant, NXP Semiconductors
Prashant Goyal, NXP Semiconductors
Shubhra Singh, NXP Semiconductors
Vigyan Jain, NXP Semiconductors
CADV-3
AMS Macro Liberty Timing Model Characterization Using Liberate AMS
Siva Mandalapu, AMD
Parameshwar Goud Lavva, AMD
Rajni Dhiman, Cadence
Filzer Kummudiyil, Cadence
CADV-4
Methodologies for Efficient EMIR Signoff Performance Using Voltus-XFI
Lisa Chu, Intel
Maharshi Solanki, Intel
Richa Agrawal, Intel
Luis Abreu, Intel
CADV-5
Advancing Design and Verification of Mixed-Signal Systems Through Cadence Virtuoso ADE - MATLAB/Simulink Integration Workflows
Jahnavi Dhulipala, MathWorks
CADV-6
Minimizing Pre vs. Post Layout Simulation Mismatch in Analog Design Using Virtuoso DI
Rajeev Singh, STMicroelectronics
Devendra Gupta, STMicroelectronics
Gautam Kumar, Cadence
Vishesh Kumar, Cadence
CADV-7
Efficient and Robust Method for Floating Gate and Leakage Current Checks in Analog/Mixed Signal SoCs
Guruprasad Bhaskar, Qualcomm
Vivekanand Malkane, Qualcomm
CADV-8
Accelerating High Sigma Analysis Using Cadence Fast Monte Carlo (FMC) Technology
Siva Charan Nimmagadda, AMD
Hari Bilash Dubey, AMD
Sasi Rama Subrahmanyam Lanka, AMD
Ryan Baek, AMD
Mohammad Anees, AMD
Badrinarayan Zanwar, Cadence
CADV-9
Digital Design Advancement with AI
Design Convergence with Superior QOR in Shorter Design Cycle Using AI/ML Methodology in APR Flow
Madhumati Angadi, Intel
Shubham Thakare, Intel
Utpal Kar, Intel
Anuj Soni, Intel
AI-2
Productivity and PPA Exploration Using ML-Driven Automated Flow
Deepika Madaan, STMicroelectronics
Renato Castellan, STMicroelectronics
Harshal Ambatkar, Cadence
AI-3
Leakage Reduction with AI-SYN Cadence Cerebrus Machine Learning Technique
Supreeth S, Mediatek
Madhavika Agarwal, Mediatek
AI-5
ML-Based PPA Exploration to Achieve the Best Design KPIs
Ramanamurthy Pusuruli, Intel
Ashwani Sharma, Intel
Guneet Singh, Intel
AI-6
Digital Design and Implementation
Achieving Best-in-Class PPA with Faster TAT for Arm Core
Tamal Sinha, Samsung
Chandrasekhar Dadu, Samsung
Lokesh Jigalur, Cadence
Karthik Arlithaya Delampady, Cadence
DDI-1
Impact of Mixed Placer on Complex Designs QOR and TAT in N7 and N5 Nodes
Veeresh Huded, Marvell
Harishchandra Yadav, Marvell
Annapurna Raina, Marvell
Pavan Kumar Shashindra, Marvell
DDI-10
Solving the Partition Puzzle - Pushing Performance on the Latest Generation Arm Cortex-X CPU Using Cadence Implementation Suite
Abhishek Sampagavi, Arm
Pavan Kumar Kuragayala, Arm
Akash Viswanath, Arm
Naga Yashas S, Arm
DDI-2
Riots of Color
Aditya Mathur, Arm
DDI-3
Implementation of DCLS in Safety-Critical Automotive Designs
Anurag Kinger, Qualcomm
Manish Mittal, Qualcomm
Jitendra Jain, Cadence
Apoorva Amdapurkar, Cadence
Dennis Wong, Cadence
DDI-4
PPA and TAT Improvements on High-Frequency CPU Core Design Using Innovus
Naveen Kumar, Intel
Priya Gupta, Intel
DDI-5
A Novel Method to Early Estimate and Optimize Signoff Power Using Joules
Dilsukh Nehra, Analog Devices
Sreejith K, Analog Devices
DDI-6
Enabling Low Area High-Performance Hybrid LBIST Using Elastic CODEC Solution in Safety Critical SoCs
Nitesh Mishra, Texas Instruments
Vidyut Singh, Texas Instruments
DDI-7
3D Partitioning and Placement for Next Generation 3D-ICs Using Integrity 3D-IC Platform for Multi-Chiplet Design
Sagar Dhule, Cadence
Chinthamani Jagannath, Cadence
DDI-8
Conformal-Based Automated Flow for Complex Physical Aware ECO in Automotive SoCs
Avneep Kumar GOYAL, STMicroelectronics
Satinder Malhi, STMicroelectronics
DDI-9
Digital Design and Signoff
Inter-Power Domain (IPD) Timing Signoff Using Tempus-IPD
Bharath Tarikere Vijayakumar, Nvidia Graphics
Ulhas Kotha, Nvidia Graphics
Mahesh D. Sadhankar, Cadence
Arvind Veeravalli, Cadence
Pawan Deep Gandhi, Cadence
Daksh Bakshi, Cadence
DDS-1
Accurate Modeling of Aging Effect with Advanced Aging Characterization Flow
ManigandeshwaranM, Arm
Satheesh Balasubramanian, Arm
Narcisse Ouedraogo, Arm
Madhulika Kaki, Arm
DDS-2
Closing Loop Between Bottom-Up and Top-Down STA Flows - An Effective Substitute for Full-Chip FLAT STA
Shourya Shukla, Marvell
Sushant Hajare, Marvell
Harshit Jaiswal, Cadence
Sharath A C, Cadence
DDS-3
Effectively Using Tempus ECO to Tackle Large Functional ECOs in the Signoff Stage
Aswin P P, Texas Instruments
Sanjana Sundaresh, Texas Instruments
Atul Garg, Texas Instruments
Ajoy Mandal, Texas Instruments
Ashwini Kulkarni, Cadence
Srikanthan M, Cadence
DDS-5
Big Die SOC Timing Signoff with Tempus BM/DSTA
Tusharkant Mishra, Samsung
Theertha Mp, Samsung
Praveen Kumar Gontla, Cadence
Manish Tikyani, Cadence
Aniket Pramod Deshmukh, Cadence
Ajay Sahoo, Cadence
DDS-6
Early Timing Closure by Leveraging Pessimism from Timing Analysis Using Cadence Tools
Shuchita Kaila, Texas Instruments
Sriraj Chellappan, Texas Instruments
Tapsir Shaikh, Texas Instruments
Gokul Sabada, Texas Instruments
Malav Shah, Texas Instruments
Krishna Panda, Texas Instruments
DDS-7
IP/Subsystem Verification: Performance and Smart Bug Hunting
Formal Property Verification and Performance Analysis for IP
Neetu Goel, NXP Semiconductors
Nandini Mudgil, NXP Semiconductors
Anshul Singhal, Cadence
IP-1
Leveraging Formal Solution/Flow Approach at SoC for On-Time Quality Tapeout
Ranjana Tiwari, STMicroelectronics
Anshul Singhal, Cadence
IP-10
Enabling Accelerated Jasper CDC Analysis
Anurag Choudhury, Texas Instruments
Anuvrat Srivastava, Texas Instruments
IP-11
Effective Formal Deadlock Verification Methodologies for Interconnect Design
Sachin Kumar, Arm
Rajesh C M, Arm
IP-2
Formal Flow for Deadlocks-Free FSMs
Mahesh Soni, Qualcomm
Nitin Neralkar, Qualcomm
IP-3
Machine Learning Techniques for Improving the Performance Metric-Driven Verification of SSDs
Kannusamy M, Samsung
Sundararajan A, Cadence
Prashanth A, Cadence
IP-4
Analysis Based on Verification of Intel’s PCIe design Stack using Cadence Denali Triple Check
Shreesha M Sathyanarayan, Intel
Mohan K Rao, Intel
IP-5
A Case Study on Scalable SV-UVM based Test bench for Verification of UniPro2.0 & UFS4.0
Piyush Tankwal, Samsung
Arnab Ghosh, Samsung
Piyush Agnihotri, Samsung
Mukesh Gandhi, Samsung
Vishnu Prasad K V, Cadence
IP-6
A Neoteric Verification Approach for Standalone DPIN Adapter Design Using Cadence USB4 VIPs
Karthikeyan Ganesan, Mediatek
Vinayakumar BH, Mediatek
Dhanyashree TS, MediaTek
Rewin Edwin, Cadence
IP-7
High-Quality Design Signoff with Jasper Structural and Auto Formal Checks
Vishnu Haridas, Intel
Mansi Rastogi, Intel
Amrut S Jigajinni, Intel
Guruprasad Timmapur, Intel
IP-8
Automotive MCU Power-Aware SoC Verification with Mixed-Signals and UPF
Hironori Tanaka, Infineon
IP-9
PCB and System Design and Analysis
Advance Techniques to Accelerate PCB Design into the Fabrication/Assembly Phase
Ponraj M, Sanmina-SCI
PCB-2
Sigrity: Automotive Ethernet Compliance Analysis
Parveen Jayamurthy, VALEO
PCB-3
Methodologies to Prevent IC Failures due to Thermal Issues
Suresh Kumar S, BigCat Wireless
PCB-5
Thermal Aware Power and Rail Analysis flow at Die Level Using Voltus and Celsius
Anubhav Johri, Analog Devices
Bijaya Dash, Analog Devices
Anusha Murthy, Analog Devices
Kaushik Kandukuri, Analog Devices
Ratnakar Bhatnagar, Cadence
Karthik Ramalingam, Cadence
PCB-6
Useful Options Available in Allegro to Increase Productivity
Srinivas Reddy, Intel
Shylaja K.S, Intel
Singaravelan V, Intel
PCB-7
ECAD MCAD Library
Srinivas Reddy, Intel
Srinivasa Prabhakar, Intel
Arunkumar Ramachandran, Intel
PCB-9
System Design and Verification: Emulation and Prototyping / Flows
Effective System validation Using Dynamic Duo - Palladium and Protium
Ponnambalam Lakshmanan, Analog Devices
Aditya Ingawale, Analog Devices
Goutham S, Cadence
Anil Kumar, Cadence
SDVE-1
Hybrid Pre-Si Validation Methodology for Heterogenous Adaptive SOCs
Alok Mistry, AMD
Raghul R, AMD
Anil Kumar Av, AMD
SDVE-2
Achieving Acceleration Using Z2 for DFT
Pragati Mishra, Arm
Jitendra Aggarwal, Arm
Goutham S, Cadence
SDVE-3
Accelerated SoC Bus Performance Verification Using Traffic Generator and Monitor on Palladium
Drippin Reagan Sargunaraj, Samsung
Shashank N, Samsung
Sarang Kalbande, Samsung
Naveen Kumar V, Cadence
SDVE-4
Left Shift Catching of Critical Low Power Bugs with Formal Verification
Madan Kumar R, Qualcomm
Manish Kumar, Qualcomm
Srobona Mitra, Qualcomm
Madhusudhana Lebaka, Qualcomm
SDVE-5
Media Performance Validation in Emulation and Post-Silicon Using Perspec
Suresh Vasu, Intel
Vinit Shenoy, Intel
Joydeep Maitra, Intel
Nithin Venkatesh, Intel
SDVE-6
A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SoC
Harshal Kothari, Samsung
Eldin Ben Jacob, Samsung
Sriram Kazhiyur Soundarrajan, Samsung
Somasunder Kattepura Sreenath, Samsung
SDVE-7
Transceiver Datapath Verification on Palladium Z1 Using JESD Accelaratable VIP
Harikrishnan Ananthanarayanan, Analog Devices
Mahesh R Varma, Analog Devices
Neenu Thomas, Analog Devices
Akshay Godse, Analog Devices
Pramoda Revanasiddappa, Synapse Design
SDVE-8
Smart Palladium Regression Run Management Using vManager
Nithin Sai Padi, Cadence
SDVE-9
System Verification: Advanced Verification Methodology
Best Practices and Formal Signoff Dynamic Clock Gating Verification
Maruthi Srinivas Narasimhan, Samsung
Shriharsha Koila, Samsung
Vaibhav Kumar Chouksey, Samsung
SVA-1
NXP_Exhaustive Formal Datapath Verification Of RISCV-based Floating Point Unit
Atishay Jain, NXP Semiconductors
Sachin Miglani, NXP Semiconductors
Sourav Roy, NXP Semiconductors
Anshul Singhal, Cadence
SVA-2
Verification Signoff of a Next-Gen CPU Using a Combination of Dynamic and Formal-Based Techniques
Karthik Rajakumar, Texas Instruments
Pooja Madhusoodhanan, Texas Instruments
Bhavya Dasari, Texas Instruments
Devi A, Texas Instruments
SVA-3
Boosting Debug Productivity by 2X Using Indago
Sundar P H, Western Digital
Rajmohan S, Western Digital
Manisha V, Western Digital
Sundararajan A, Cadence
SVA-4
PCI Express Inter-Operability Flow & Verification Using Cadence PCIe TripleCheck & Pipe Phy Monitors
Akhil Kumar G B, Marvell
Ashutosh Rawal, Marvell
Sattibabu Peddireddi, Marvell
Ezra K, Cadence
SVA-5
Getting the Most of UVM-e Extensibility to Increase Verification Productivity Using Cadence Flow
Himanshu Rawal, Intel
SVA-6
Resilience Property of Xcelium ML Flow for Faster Coverage Closure
Ratan Deep, Samsung
Het Shah, Samsung
Arun K.R, Samsung
Harsh Setia, Samsung
Sundararajan A, Cadence
SVA-7
Comprehensive Verification Signoff Using Simulation and Formal Methods in the Vmanager Platform
Vishal Dalal, Infineon
Basavaraj Naik, Infineon
SVA-8
Validating ASIL-D Requirements Using Cadence FuSa Solution
Prashantkumar Ravindra, Analog Devices
Praneeth Uddagiri, Analog Devices
Veera Satya Sai Gavirni, Analog Devices
Siri Rajanedi, Analog Devices
Mangesh Pande, Cadence
Vinay Rawat, Cadence
SVA-9