CadenceLIVE Europe – OnDemand
Academic and Entrepreneur Showcase
Design of Low Phase Noise Amplifier with 50GHz Bandwidth
Vijayalakshmi Surendranath Shroff, University of Paderborn
AC01
gm/ID Based Circuit Design with the Expert Design Plan (EDP) Toolbox
Matthias Schweikardt, Reutlingen University
AC02
Integration of Piezoresistive Parameters into BSIM Models
Kim Allinger, Hamburg University of Technology
Matthias Kuhl, University of Freiburg - IMTEK
AC03
Process Design Kit Adaptation for Vertical Nanowire MOSFET in an IC Design Flow
Pavan Kubair, Lund University
Arturo Prieto, Lund University
Lars Ohlsson Fhager, Lund University
Marcus Sandberg, Lund University
Joachim Rodrigues, Lund University
AC04
Reinforcement Learning Environment for Circuit Sizing in a Transformed Action Space Based on Cadence Spectre
Yannick Uhlmann, Electronics & Drives (HSRT)
Jürgen Scheible, Electronics & Drives (HSRT)
AC05
Semi-Automatic Test Bench Generation and Parameter Extraction Tool Using Cadence SKILL
Alexander Meyer, RWTH Aachen University
Leon Wiehs, RWTH Aachen University
Ralf Wunderlich, RWTH Aachen University
Stefan Heinen, RWTH Aachen University
AC06
Specialization and Performance Optimization of a TTA Processor for Communication in Harsh Environments using Timing Speculation
Malte Hawich, University of Hannover
AC07
Introducing Bifrost Communications
Jesper Bevensee Jensen, Bifrost Communications
AC08
Introducing Wiyo Technologies
Patricia Fermin de Moreno, Wiyo Technologies
AC10
Introducing Synthara
Manu V Nair, Synthara
Alessandro Aimar, Synthara
AC12
Introducing Fleeptech
Giorgio Dell'Erba, Fleeptech
AC13
Introducing Lotus Microsystems
Ahmed Ammar, Lotus Microsystems
AC14
Introducing SkyCore Semiconductors
Pere Llimos Muntal, Skycore Semiconductors
AC15
Introducting DeepDetection
Colin Burnham, DeepDetection
Jose Gabriel Macias, DeepDetection
AC16
Automotive & IP
Development of Radar Algorithm for the Tensilica Processor
Andy Heinig, Fraunhofer IIS/EAS
AUTO01
FISH: Fault Injection Self-Detecting Chip for Analyzing Radiation Effects on Memory Elements
Gia Bao Thieu, TU Braunschweig
Moritz Weißbrich, TU Braunschweig
AUTO02
Functional Safety Analysis: Deal with Integrators Customizations
Francesco Lertora, Cadence
Sanjay Singh, Texas Instruments
Rajat Mehrotra, Texas Instruments
AUTO03
ISO26262 Functional Safety Mechanism Designed in GlobalFoundries' 22FDX Automotive Digital Design Flow
Falk Tischer, GlobalFoundries
Nidish Gaur, GlobalFoundaries
AUTO04
Pre-Silicon Functional Safety Verification Strategy - Mixed-Signal ICs
Silvia Strähle, Infineon Technologies
Rania Sanaa, Infineon Technologies AG
Joice George, Infineon Technologies AG
AUTO05
Ultra-Low-Power Implementation of Tensilica Fusion F1 Processor
Sven Brunmark, Xenergic
Babak Mohammadi, Xenergic
AUTO06
Verifying ECCs used in Safety Critical Designs with Formal
Aman Kumar, Infineon Technologies
Daniel Gerl, Infineon Technologies
AUTO07
Cloud
Accelerate Time to Results with Flexible Compute Choices on AWS
Eran Brown, AWS
CL01
Cadence Design Flow for Advance RF/Mixed-Signal ICs
Savvas Sgourenas, MEICSi
CL02
Scaling to 1 Million+ Cores to Reduce Time to Results, with up to 90% Discount on Compute Costs
Ludvig Nordstrom, AWS
CL03
Using Cadence in the AWS Cloud
Shawn Ruby, Ruby Cherry EDA
CL04
Computational Fluid Dynamics
AeroDelft CFD Projects
Francesco Granata, AeroDelft
Abel Versloot, AeroDelft
CFD01
Investigating the Circumferential Inhomogeneous Flow of Centrifugal Compressor Using Cadence CFD
Loic Reymond, Institute of Jet Propulsion and Turbomachinery - RWTH Aachen University
CFD02
Predicting Reentry Trajectories Into the Atmosphere of Mars
Maximilian Maigler, Universität der Bundeswehr München
Valentina Pessina, UniBw Munich
CFD03
Custom/Analog Design
AgeMOS2 BTI Model for Aging Simulations in Advanced Nodes
Andre Lange, Fraunhofer IIS/EAS
CAD01
Aging Models and Simulation for RF and Analog Applications
Ofer Tamir, Tower Semiconductor
Alex Kozhekin, Tower Semiconductor
CAD02
Design Verification for X-FAB Combined Flash and EEPROM IPs – SpectreX vs. APS Benchmark
Marco Sommer, X-FAB
Alexander Gittel, X-FAB
CAD03
Fault Simulation of X-FAB Memory IPs Using Legato Reliability
Christophe Sabatier, X-FAB
Andrey Karavaev, X-FAB
CAD04
Improve MC Analysis Performance Using Spectre Native Fast MC Solution for Advanced Nodes
Dinesh Babu Rajendran, Intel
Puneet Singh, Intel
CAD05
Layout Verification and Optimization by Pattern Matching
Jaap van der Sluijs, NXP
CAD06
Multi-Stage Trimming Flow for High-Precision Analog Circuit Design
Florin Burcea, Bosch Sensortec GmbH
Lucian Stoica, Bosch Sensortec GmbH
CAD07
PG Pcells- A Correct by Construction Power and Ground Distribution Strategy
Gaurav Masiwal, IC Mask Design
Cíarán Whyte, IC Mask Design Ltd.
CAD08
Statistical Reliability Simulations with the Cadence Virtuoso ADE Product Suite
Leonard Heiss, Intel
Andreas Lachmann, Intel
Clement Melen, Intel
Reiner Schwab, Intel
CAD09
Utilizing Virtuoso CLE (Concurrent Layout Editor) Tool to Reduce Critical Layout Design Time and Improve Productivity
Jiri Dak, Analog Devices
Eduard Raines, Analog Devices
CAD10
Virtuoso Design Planner Analysis and Design Intent, A Way Ahead Than Traditional Implementation for Chips Design: The New Methodology for the Next MSoT Smart Power (BCD) Designs
Livio Fratantonio, STMicroelectronics
Massimiliano Innocenti, STMicroelectronics
Riccardo Guglielmo, STMicroelectronics
Stefano Basile, Cadence
Jonhatan Elias Olave, Cadence
CAD11
Voltus-XFi – Efficient EMIR Methodologies for Signoff
Luis Abreu, Intel
Lisa Chu, Intel
Maharshi Solanki, Intel
Richa Agrawal, Intel
Ayan Roy Chowdhury, Intel
CAD12
Voltus-XFI - Next Generation of EMIR Flow
Qiang Wang, NXP
Kai Schiller, Cadence
CAD13
Digital Design & Signoff
A Novel Approach of Reducing Power Consumption of Design Using Joules RTL Low-Power Solution
Chandra Sekhar Naik Banavath, Infineon Technologies
Jibanjeet Mishra, Infineon Technologies
DDS01
Cerebrus and Innovus Mixed Placer as Key Approaches for a Complex 7nm Design
Thomas Haase, Renesas
DDS02
Cerebrus PPA Optimization on the Next Generation of High-End Microcontroller CPU Core
Olivier Uliana, STMicroelectronics
DDS03
Design Enablement of 2D/3D Thermal-aware Analysis and 3-dies Stack
Mohamed Naeim, Cadence
Dragomir Milojevic, IMEC
DDS04
Early Power Analysis Using Joules
Shane Gallagher, Analog Devices
DDS05
Imec IClink – Preparing our Digital ASIC Design Implementation Teams for Future Advanced Node Projects
Geert Vanwijnsberghe, IMEC
Ilse Vos, IMEC
DDS06
Lithography Hotspot Detection with Cadence LPA tool: from P&R to Signoff
Lise Doyen, STMicroelectronics
DDS07
Timing Constraints Consistentency Checked with Conformal Litmus
Jörg Lindemann, Finisar/II-VI/Coherent
DDS08
Using Physical Synthesis and Physical Tools in RISC-V IP Development Flow
Premysl Vaclavik, Codasip
DDS09
Mixed-Signal Design
Advanced Layout Implementation of Digital Blocks in Analog Environment
Yan Woon Chong, Intel
MXD01
Advancing Design and Verification of Mixed-Signal Systems through Cadence Virtuoso ADE - MATLAB/Simulink Integration Workflows
Ganesh Raj Rathinavel, Mathworks
Andrew Beckett, Cadence
MXD02
Automatic Generation of Multiple GF-22FDX OpAmp Variants and Layouts in the Virtuoso Suite by Incorporating ID-Xplore of Intento Design with IIP of Fraunhofer
Benjamin Prautsch, Fraunhofer IIS/EAS
Uwe Eichler, Fraunhofer IIS/EAS
Ramy Iskander, Intento Design
Jose Bonan, Intento Design
Anoukis Boutros, Intento Design
MXD03
Contributions to Accellera UVM-AMS Standardizations by Renesas and Cadence
Peter Grove, Renesas
Steven Holloway, Renesas
Shekar Chetput, Cadence
Tim Pylant, Cadence
MXD04
From Spec to Virtuoso
Juan Verdu, Texas Instruments
Angelika Keppeler, TI
Jerry Chang, TI
MXD05
Improving Performance of Analog/Mixed-Signal Layouts with Voltus-Fi
Guenter Haider, Infineon
Adrian Bertsovskyi, eesy-ic
MXD06
Investigation of FastSpice Engine SpectreFX
Mudasir Bashir, Infineon Austria AG
Haiko Morgenstern, Infineon
MXD07
Model Validation Using Virtuoso ADE Assembler/vManager
Peter Grove, Renesas
MXD08
Virtuoso ART Automated Analog/Digital Routing in Samsung Advanced Nodes and Mature Nodes
Sungsik Park, Samsung Electronics
Seungil Chai, Samsung Electronics
K.B. Lee, Cadence
Sanjib Ghosh, Cadence
MXD09
PCB & System Analysis
A 35GHz, Multi AFE & SerDes Interfaces Device Substrate Design for Satellite Communication Systems
Eran Rotem, Satixfy
Bojidar Avdjiiski, Satixfy
PCB01
Design Challenges for Rugged PCBs
János Lazányi, PCB Design
PCB02
Geometry Pre-Processing with ANSA for Clarity EM Analysis
Christos Liontas, BETA CAE Systems SA
Athanasios Papadopoulos, BETA CAE Systems SA
PCB03
Optimize Faster High-Speed Vias Using AI-Enabled Optimality Explorer
Kristoffer Skytte, Cadence
Natalia Floman, Infineon
PCB04
Optimizing an Bluetooth Antenna for Industrial IoT Applications
Dirk Mueller, FlowCAD
PCB05
Productivity enhancement for Allego PCB and IC Packaging
Rolf Nick, FlowCAD
PCB06
Structured Thermal Analysis on a Real Design Example
Tobias Best, ALPHA-Numerics
PCB07
Thermally Aware High-Power Inverter Board for Battery-Powered Applications
Prospero Lombardi, STMicroelectronics
PCB08
RF & Systems
A Comprehensive Design Flow for IC and Packaging for a 28GHz WiFi System
Fabian Hopsch, Fraunhofer IIS/EAS
RF01
A Fully Automated and Foundry-Independent Quality Assurance Platform for Cadence Process Design Kits
Anton Datsuk, IHP GmbH
RF02
Cadence Quantus Incremental Technology Flow for Extraction of Parasitics Between Packaging and IC
Lucas Brusamarello, NXP
Sylvie Parmantier, Cadence
Nikita Nikitenko, Yandex
RF03
Cadence RF IC Design Reference Flow at Samsung
Soonkeol Ryu, Samsung Electronics
RF04
Design of a Multiband Antenna System for an IoT Device Using IGNION ONE mXTEND Antenna Booster
Agusti Padros, Ramon Llull University
Sergi Balart, Ramon Llull University
RF05
GF Fotonix PEX EMIR Enhancements
Shanti Siemes, GLOBALFOUNDRIES
Ingo Kuehn, GLOBAL FOUNDRIES
RF06
Linearization of RF Frontends in EDA
Markus Loerner, Rohde & Schwarz International
RF07
Short-loop ASIC-Package Co-Design with Virtuoso Design Platform and Allegro Package Designer
Goeran Jerke, Robert Bosch GmbH
Sascha Hoefer, GlobalFoundaries
Chenbo Liu, GlobalFoundaries
Marcel Mueller, Robert Bosch GmbH
Vinko Marolt, Robert Bosch GmbH
RF08
Understanding On-Die Thermal Mismatch with Legato Reliability and Celsius
Stephan Endrass, Texas Instruments
Sudarshan Udayashankar, Texas Instruments
Mayank Jain, Texas Instruments
RF09
Virtuoso RF Co-Design Flow - S-parameter Extraction with Clarity 3D on the STM32WB
Romain Pilard, STMicroelectronics
Michel Ayraud, STMicroelectronics
Salvatore Cosentino, STMicroelectronics
RF10
X-FAB millimeter wave transmission lines components kit for 130nm RF SOI technology
Fadi Zaki, X-FAB
RF11
X-FAB RF Reference Kit Showing EM Simulations with EMX for 130nm SOI Technology
Smriti Joshi, X-FAB
RF12
Verification
Memory Verification in UVM made simpler using Algorithms and the role of vManager
Sougata Bhattacharjee, Samsung
VER01
A Highly Efficient Pre-Silicon Development Platform for PCIe Drivers of a SoC
Christian Bruel, STMicroelectronics
Salah Hama, STMicroelectronics
Vincent Motel, Cadence
Jeremie Chaboud, STMicroelectronics
VER02
Accelerating Debug and Signoff for RISC-V Processors Using Formal Verification
Ashish Darbari, Axiomise
VER03
Accelerating Safety and Security Features Verification of Specialized Processors with the Jasper Functional Safety App
Sedat Sayar, STMicroelectronics
Samuel Tomasi, STMicroelectronics
Jean Paul Henriques, STMicroelectronics
VER04
ATPG Scan Tests Runtime Improvement with Cadence MCE (Multi-core Engine)
Priyanka Murthy, NXP
Cezar De Oliveira Dos Santos, NXP
VER05
Creating a Simulation Hybrid for SoC Verification with Helium
Vincent Motel, Cadence
Isabelle Sename, STMicroelectronics
Houcine Oucheikh, STMicroelectronics
Bruno Moison, STMicroelectronics
Jerome Berliat, STMicroelectronics
VER06
Jasper CDC Analysis of Satellite Tracker RTL
Igor Mohor, u-blox
VER07
Portable Stimulus Test Development and Execution on ATE systems
Marcus Schulze Westenhorst, Advantest Europe
Markus Bücker, Advantest Europe
VER08
PSS Model as a Key Point to Prepare System Test from Early IP Verification
Claire Bonnet, STMicroelectronics
Claire Verilhac, STMicroelectronics
Solene NAVARO, STMicroelectronics
VER09
Real-Time Evaluation of 60 Powerline Communication Modems Using the Protium S1 FPGA Platform
Tobias Stuckenberg, University of Hannover
Holger Blume, University of Hannover
VER10
Setting-up a Jenkins Continuous Integration Flow on the Jasper Formal Verification Environment
Gregory Faux, STMicroelectronics
Laurent Martin-Borret, STMicroelectronics
VER11
Using Cadence Fault Campaign Manager for Fault Grading
Cezar de Oliveira dos Santos, NXP
Guillaume Peccatte, Infineon
Viktor Preis, Cadence
Kiran Kariyannavar, NXP Semiconductor
VER12