Library characterization for an advanced node design is a compute-intensive task -- ideal for a scalable and flexible cloud. In this presentation M31 will describe a Library characterization methodology that enabled 5x faster delivery using Liberate on Cadence-managed CloudBurst.

Historically, physical verification jobs have been very compute- and memory-intensive. Silicon designers are often resource-challenged to run physical verification on designs that can consume 1000s of CPU cores and require multiple days to complete. The new Pegasus TrueCloud enables designers to run physical verification jobs from on-prem compute resources onto the cloud and has a massively scalable architecture that can reduce design cycle time.

Circuit simulation is one of the key workloads for both AMS and logic design. Configuring and matching infrastructure in the cloud is key to customers getting the best performance and value with this workload. We will discuss best practices on setup and resource selection of Azure resources to run Spectre X on the cloud.

Realizing CFD Vision 2030: Progress and Future Plans within the Aerospace Community. The NASA-commissioned Computational Fluid Dynamics (CFD) Vision 2030 report, originally published in April 2014, laid out a compelling vision of the predictive numerical simulation capabilities required to support a broad range of envisioned air and space vehicles in the notional 2030 timeframe. The study also included a comprehensive CFD technology roadmap, which has become the definitive standard driving CFD development around the world. This presentation will focus on the activities of the AIAA-sponsored CFD2030 Integration Committee (IC), which has been established to promote and advance the objectives of the Vision study. These activities include a thorough review and update of the technology development milestones and demonstrations outlined on the roadmap, a focus on defining the details of critical CFD Grand Challenges, and efforts to engage the aerospace and CFD communities through AIAA-hosted conference events, such as Forum 360 panel discussions. Finally, related activities closely aligned with the CFD2030IC, including CFD validation and prediction workshops, as well as efforts to advance Certification by Analysis, will be also discussed.

Output-based mesh adaptation is achieved by coupling the MIT SANS finite-element solver and metric optimization with the Pointwise mesh generator. The interface between SANS and Pointwise is a fine-grain point cloud of sizing requests that drives the Pointwise meshing algorithm.  Viscous adaptation is achieved via a hybrid approach where sizing requests drive isotropic refinement and viscous layers are apriori generated. Adaptation results are shown for 2D inviscid and viscous airfoil cases starting from extremely coarse initial mesh resolution, as well as select 2D hypersonic test cases.

Cadence presents a new technology based on advanced numerical algorithms that yield high scale-resolving accuracy on low-cell-count grids within fast turnaround times. The solver is fully integrated into an end-to-end platform that streamlines the geometry preparation, mesh generation, simulation, and co-/post-processing, leveraging the power of GPU infrastructures with minimal user intervention

Supported by DOE's INCITE program, we are performing a wall-resolved large eddy simulation (WRLES) of the NASA Common Research Model (CRM)  high-Lift Configuration on Summit. Progresses in many areas are needed to enable this undertaking: adaptive high-order methods, high-order mesh generation, implicit solution algorithms, and efficient implementation on extreme scale CPU/GPU clusters. Preliminary results will be presented.

We present the approach, results and validation of modeling hypersonic reacting flows, specifically reentry of spacecraft into Earth, Mars and Titan atmosphere using advanced computational fluid dynamics. The models include dissociation behind the shock wave infront the vehicles as well as ablation effects on the thermal protection system. We compare fully and semistructured meshing approaches and results obtained by commercial (Ansys Fluent) and Open Source software (OpenFOAM with community packages). The validation is carried out using experimental data and existing publications for specific flow problems such as test geometries and several experimental and in-operation vehicles.

To balance our need for scalable PDK development process with our commitment to high quality, we improved our QA capabilities with a fully automated test flow of the back-annotation with Cadence Virtuoso ADE Product Suite. Our first approach was to parse the modeling standards documentation and led us to eventually decide to run the full simulation instead. This new paradigm brought us to the next step: the necessity to generate schematic testcases automatically and the Cadence function schCreateWire was a great help in this endeavor. We also needed to use the WaitUntilDone function, however it was not available in ADE XL so we moved to ADE Explorer/Assembler. The documentation for the GUI part was very helpful. However, we had to dig a little deeper for information outside of the GUI, which was what we needed for our automation, especially when we wanted to enable the interpreted labels that hold the back-annotation values.

Complete automation of the analog IC design flows is a concept that has been debated for decades. While total automation is still a distant goal, the EDA community has focused on automating elements of the design process, such as placement. Placement is crucial. Correct placement of design components in layout is an important element for success of the overall design. It was important in the past, it is important now and it is even more important in the future. Advanced node placement is precise, and time consuming. The Design Rules complexity is constantly increasing and becoming more interdependent making analog placement in advanced processes even more challenging. The main question of any EDA vendor is how to simplify the task of getting high quality, deterministic placement results? What is easy way to navigate through enormous amount of placement rules? How effectively provide an environment to simplify modern complex placement tasks? To answer some of these questions, snapPattern technology has been introduced in IC20 to help solve advanced nodes placement complexities, minimize and in some cases eliminate DRC errors and create DRC clean layout prior to full layout completion. In this presentation we will introduce IC20 snapPattern technology for advanced nodes. We will demo how to define snapPatterns and how they work to achieve precise, correct-by-construction grid-based placement. Then we will show how we utilize this snapPattern technology for mature node tasks such as the grided placement of chip level design components. We will demonstrate how complex, time-consuming bump placement, for example, can benefit from the assistance of custom snapPaterns. By defining a placement grid using snapPatterns, we can create a correct by construction bump placement in less time. We will also demonstrate how customizable (by project or by user) placement grids for different regions of the design can in some cases achieve 10x placement productivity gain. SnapPattern based, simplified placement allows any project member to be proficient in placement/layout of any design element.

In the ever-shrinking world of chip design, designers are on the lookout for fitting more geometries in a limited space. Design Rule Checks (DRC) enforce that net shapes maintain minimum spacing. The minimum spacing is also dependent on the difference in voltage values of these net shapes. Conventional methodology, of difference in voltage calculation on net shapes and subsequent spacing checks, leads to pessimistic results. For various functionally correlated nets in the design, it is possible to relax the minimum spacing requirement thereby making the layout compact in terms of space utilization. The paper describes a method to reduce pessimism in voltage-dependent DRC for functionally correlated nets. The described method covers an end-to-end solution, where dynamic voltage specs are derived from simulation results then implemented in the layout, and subsequently gets validated before running the signoff DRC check. The method also includes debuggability of the violations reported by the signoff DRC run, which considerably improves the usability of the solution for end-users.

Advanced node challenges contributed significantly in time and iterations to complete design cycle especially for complex custom mixed signal designs for the IPs which go into reconfigurable computing systems like FPGA chips and common standard methodologies are not able to address new design challenges, improve time to market and enhance the quality of products. 

Based on the layout planning and design complexity, multiple designers work in parallel in order to meet the critical projects requirement and deadlines. In existing layout flow, design manager who is handling top level layout will do the layout partition and decide  the free area for other layout designers working on same project , other designer would proceed on different cell view and complete task in allocated area within locally created  library and later share his library path to design manager. Since in existing flow multiple designers cannot work together and edit on single layout cell view, therefore it is very time consuming for design manager to complete all task of planning, assigning works, integration and repeat the same task at various stages of layout developments.

Physical signoff is very challenging during the tape out week of the development cycle. At this stage, in existing layout methodology, there is no way where layout can be selectively partitioned and assigned to multiple designers in order to reduce the overall task and to fix massive number of DRC errors.

Above problem areas and design complexities are drastically reduced by novel way of utilizing the Advanced Virtuoso Concurrent Layout Editor (CLE) in layout development.

Virtuoso CLE provides an editing environment that lets several designers to work concurrently on the same design at the same time, helping in cutting long design cycles and improving productivity.  In this paper, two use cases are discussed where we leveraged area and layer-based CLE methodologies and its benefits during routing and expediting DRC sign-off.

Use Case-1

CLE is majorly used for fixing the DRC for a bigger block with partitions based on area/layers. Along with DRC fixes we can make use of CLE in routing phase also if the design meets some specific requirements. Here in AMD we identified such designs to leverage the advantage of CLE and complete the routing in shorter time without compromising on quality of the design. Design requirements are explained in this paper with example which are implemented with CLE and reduced the time to market. 

  An IO block, which is compatible with CLE, designed with conventional way of routing, would take at least 8 working days for 1 resource. When we use CLE with 3 resources, all the routing and integration was completed within 3 working days. This resulted in reducing the overall design time. 

Use Case-2

After routing phase and LVS clean, CLE has an advantage in taking DRC fixes as well. With the advantage of Area/Layer based partitions one can fix the DRC based on requirements. With given observation area-based partitions are much helpful while fixing the base/frontend DRC, as it may need some device/block movements and drawing the flat layers. When it comes to backend DRC fixes layer-based partition gives full-advantage in reducing the design cycle. 

Before running the DRC or any Physical Verification (PV) checks for partition level edits, one should aware of the virtual memory (VM) concept and how CLE uses VM to improve the disk space utilization and makes faster in opening the design. CLE saves only incremental edits in the partition view (disk space) to make it light weighted and the master view will be loaded into VM dynamically when the cell is opened. User will see both combined in the single layout window. As partition view has incremental edits only, PV tools try to run the checks only for these few incremental edits rather than complete design, so we might get incorrect reports due to this. To avoid this issue, one need to export GDSII/OASIS with Virtual Memory Export (VME) option enabled, Cadence is providing this option on CLE canvas. The exported GDSII/OASIS need to give as an input to the PV tool. As this is multistep process and error prone. A customized inhouse PV GUI has been developed which is capable of exporting GDSII/OASIS and run selected PV check with a simple button click and helps user to make it fast with more accuracy. 

Another IO block for backend DRC fixes with initial estimate of 5 working days for 1 resource and with CLE layer based partition with 3 resources could complete all the DRC fixes within 2 working days only without compromising on the quality of the layout at any given point of time. 

Results:

CLE helped us in reducing the design cycle by a great extent in both routing and DRC fixing phase of the design in all possible blocks, which eventually helped in achieving the tape-out deadlines hassle free. Here are the results tabulated with and without CLE for set of blocks which are worked on. 

1. Inter-block level routing time reduced from 8 working days (1 resource) to3 working days (3 resources)

2. Backend DRC fixes for a top-level block signoff time reduced from 5 working days (1 resource) to 3 working days (2 resources)

Systems Engineers cover the requirements and operating conditions of analog-mixed signal circuits in a structured way at an early stage. During the development if the IC changes can happen to those requirements and operating conditions for example due to changed customer requirements. 

While in current flows the designers carry over the information from the spec to the design environment often in an unstructured way, Cadence’s Verifier together with the Setup Library Assistant offers the possibility to bring this information from the device specification to the simulation in a structured way. Through the given API functions the specification data can be pulled into the Virtuoso environment without manual interaction. In addition, a frequent sync between spec and design environment ensures that no changes are missed and the environment ensures that simulations meet the requirements under all defined operating conditions given in the device specification. Designers do not have to go and change the individual Maestro states, but changes can be applied automatically without manual effort.

A novel method for injecting faults to verify safety critical system level functions and monitors. We go over how to inject faults in the DUT and bypass the testbench. This reduces testbench complexity by reducing the number of external components and configs we need to have. This method can be extrapolated and used in a wide range of verification activities.

Design and verification of mixed-signal IP is becoming increasingly challenging with advanced-process nodes. Increasingly stringent design specifications to meet end customer demands are leading to higher design complexity. Verifying these complex designs is complicated because of evolving newer architectures, higher clock speeds , increasing design sizes due to advanced-node processes, and the exponential increase in layout parasitics. The need to accomplish verification closure in tight schedule is driving the need for faster circuit simulators which simultaneously meet the required accuracy for these designs. To meet this need, Samsung Foundry and Cadence have been keeping in tight collaboration, and as a part of such co-workings, Samsung Foundry has evaluated the Cadence's new FatsSPICE simulator, Spectre FX Simulator, on Samsung Foundry advanced node. This presentation focuses on how Cadence’s Spectre FX FastSPICE simulator was used to verify Samsung Foundry’s AMS IP with fast performance and the required accuracy. We will demonstrate how the simulator was set up and used to verify PLL, SRAM, and PCIe designs on Samsung’s latest process nodes.

The global GDP is forecasted to increase by $12 Trillion by 2030 with the advancements of ML and AI (wsj.com). SKILL coding across Cadence tools is pervasive and can unlock the power of automation in many design flows (Virtuoso, EAD, Voltus-Fi, DRD, Pegasus, etc). We are constantly looking for ways to assist our developers expedite the implementation of our PDKs with high quality in mind. We established a best practice document at GlobalFoundries to guide our analog & RF device/library developers toward “good by construction” code. But reviewing best practices is time consuming, so our approach is to automatically inform developers if their code is “best practices compliant” as they write it. A script was developed to support SKILL CDF and pcell development. Several features are checked by the script, like supporting netlisting for simulation and layout placement using VXL. Our tool leverages python to verify best practices compliance in two ways: first, by parsing a file, and second, by using machine learning for best practices that are too difficult to detect through parsing. In addition, we implemented a program to make live suggestions to developers for text completion. Developers writing in the SKILL programming language use various text editors. One useful tool to write SKILL often overlooked is the SKILL IDE. Not only is the SKILL IDE integrated into the DFII environment, but it has great customization options such as creating pop-up windows and text highlighting. These features allowed us to create an interface to our script to provide feedback to developers on their compliance with the best practices. Our tool currently covers 7 best practices and gained interest among developers to add features that can be added thanks to the versatility of our interface and the SKILL IDE. These best practices describe methods that may not cause an issue that would be immediately caught in unit testing or by Lint but may be discovered late during netlisting or further in the design process. This project resulted in a practical testing tool that developers can use when coding SKILL. As part of this work, developers felt encouraged to take a closer look at the SKILL IDE. Our Machine Learning assisted SKILL coding approach allows us to not only catch issues before they are coded but also surfaces problems that traditional test suites wouldn’t detect. This will enable significant cost savings for GF and its customers.

SKILL customizations and development leveraged the Navigator, Annotation Browser and VDR flow. The development was driven by design ECO’s which create the need to find, debug and manipulate layout design objects.

Impactful utilities include understanding the Cell Instance hierarchy and all dependencies which is essential for large designs with multiple levels of hierarchy. At the net level a utility to show net intersections, device connections and hierarchy with results displayed in the Annotation Browser is a significant aide in debugging and comprehension. For a design impacted by voltage dependent finding the nets with voltage properties or instances is made easier with a utility which groups the results in the Navigator and in a summary. If there truly is a bug, a comprehensive one click solution which packages data utility to recreate all aspects is captured. Finally, before a design is streamed out, a thoroughly set of check and fix scripts are available.  The initial motivation and hints and hacks on how to implement are also included.

Mixed-signal design and verification become increasingly challenging at 7nm and below, especially for digital and analog co-simulations. Usually, mixed signal co-simulation is required to run at higher level with large scope of analog and digital circuitries. However, the traditional flow cannot achieve the fine accuracy required by high frequency components in analog circuits. As a result, the simulator step time would be significantly reduced, and the simulation time increases tremendously, up to 1 month. Hence it is critical to improve simulation throughput and reduce resource consumption for such cases.

To address this challenge, we developed a new simulation flow using Spectre X. In this flow a single simulation environment and a single simulator are used for both analog and digital circuits. Digital RTL blocks are imported into Cadence Virtuoso schematic and connected to analog blocks. The Spectre X simulator is utilized to perform functional verifications at the transistor level. Fine time steps required by high frequency components such as VCO are accommodated in simulations. Simulation times are reduced from months to less than one week. Block level simulation and top-level functional verification can be performed in the same environment, eliminating the need of switching design flows.

In this paper, we will demonstrate the efficiency of the flow using a PLL top-level verification test bench that includes the entire analog PLL blocks and digital circuit during calibration. The VCO is composed of passive LC components with RF models. The simulation time is in the range of ~10us, and the verification is completed within one week. This flow is proven efficient for functional verification to detect potential bugs at early design phase. It reduces the design cycle and provides confidence for final design sign-off. Challenge of digital circuit debugging will also be discussed.

TI is collaborating with Cadence on the new electro-thermal DC and transient analysis in Spectre.  We start by explaining the new electro-thermal transient and DC analyses in Spectre, highlighting its potential and details of our collaboration with Cadence to improve Spectre Thermal to production quality. We address the intricacies and limitations of technology and package abstractions, before we go describe memory and CPU requirements.  

We conclude with describing our results from the electrothermal simulation of a precision amplifier, where we were able to predict

CMRR and PSRR performance.

Characterization of analog-mixed signal macros have been challenging at Intel. Liberate-AMS has been adopted for timing, pincap characterization of analog IP (AIP) due to ease-of-setup, fast run time, and SPICE like accuracy. It’s hybrid partitioning technology for timing and pincap helps in characterizing mixed-signal blocks efficiently and accurately. We open this CDN Live presentation discussing the “hybrid flow” and how it enabled balancing characterization runs between accuracy for most critical paths and agility of optimal runtime for large designs. We briefly introduce noise modeling flow together with accuracy correlation and runtime data for timing, pincap, and LVF. The tool’s versatility is availed through the flow developed by integrating it with Virtuoso ADE flexibly which provides for a greater ease of use through smake flow. The smake flow streams line the characterization data management and greatly improves the characterization flow usage within design environment. It provides designers the flexibility to quickly shift from the GUI-based to command-line-based environment to produce libraries from pre-existing setups. Finally, we conclude with recommended future improvements.

Flex Logix Technologies is a semiconductor startup designing complex AI edge inference accelerator and the leading supplier of eFPGA IP using Cadence’s Tools and Cliosoft SOS Design Management Platform to handle the complexities of product development.

Flex Logix is a reconfigurable computing company providing AI Inference and eFPGA IP solutions based on software, systems, and silicon.  Flex Logix InferX™ edge inferencing solutions provides flexible high-performance AI inference processing for less cost and lower power than GPU-based competitors.  Flex Logix is also the leading supplier in eFPGAs, EFLX, with more designs, metal stacks and configurations supported. We have been creating award winning eFPGAs for years and EFLX eFPGAs of any size can be delivered in a few days with available processes which are in 180nm down to 6nm.  Reduce power, add reconfigurability and accelerate your chips with EFLX eFPGAs.

Cliosoft SOS integration with Cadence Virtuoso provides a unique capability built right into its Library Manager. It allows project teams to track actionable values on design objects and display them like spreadsheet columns. Design teams can track actionable project metrics such as Effort Level, Percent Completed, and Completion Dates natively within the Cadence Virtuoso interface. Each custom column can be associated with a built-in function such as count, total, average, and even custom functions using Cadence Skill. This feature helps provides design team’s visibility and functionality to manage projects efficiently. It also provides Design Manager with real-time design intelligence with automatic tracking, analysis, and visualization.

The challenges of today's advanced silicon process nodes, as well as stringent performance targets, escalate mixed-signal design complexity. As these designs are created in different abstractions and design flows, exhaustive verification routines are needed to ensure functional and specfication compliant designs. Design automation workflows that scale and improve various stages of the IC development process including digital design, analog and mixed-signal design, pre-silicon verification, and post-silicon validation are critical for the success of these complex engineering tasks.  

In this presentation, Cadence & MathWorks will present the latest advancement in verification and visualization techniques through combining the MathWorks Mixed-Signal Analyzer app and Cadence ADE workflow to enable seamless data post-processing. We will also present the Simulink and Cadence Virtuoso integration workflows such as co-simulation and Simulink model export through DPI-C code generation.

From an early pioneer in DOCSIS to today’s unquestioned industry leader, Broadcom has developed the industry’s strongest and most widely deployed solutions for both head-end equipments and CPE products. Broadcom continues to lead this space and is always looking to improve design flows to achieve best performance with reduced time to market. In this session, we will talk about how Cerebrus machine learning tool works, our evaluation results, and how we are using this flow to help improve performance of our next generation chip, while also increasing engineering productivity.

As the world's leading microcontroller vendor, Renesas Electronics offers a wide selection of microcontrollers (MCUs) and microprocessors (MPUs). In order to develop these products quickly and with high quality, Renesas is always working to improve design efficiency by introducing the latest design flows, tools and by automating verification.

Recently, we adopted Cadence's Stylus digital full flow from logic synthesis to implementation and signoff, and also applied Cerebrus with machine learning optimization to both improve PPA and shorten development time, which have now been used to tapeout a high-performance MCU design. In this session, an overview of each initiative and its effects will be presented.

Between the growing complexity of technology and design, the desire to shorten time to market, and the need to significantly improve product performance with every release, the capacity of a human engineer to find best-in-class solutions in a limited time is seriously challenged. Design automation capabilities have consistently improved over time to further the cause, but arguably few of them have the ability to scale up the productivity of a human engineer as much as machine learning (ML). Apart from proof of concept, the practical problem remains on how best to leverage this technology to achieve the goals of PPA and Schedule (PPA-S), without overloading compute resources or increasing human intervention and oversight. In this session, we present how NVIDIA has deployed Cadence Cerebrus to significantly improve PPA-S of our highest performance GPU and Tegra chips, leveraging capabilities of model reuse and replay, to substantially accelerate and enhance the scope of PPA exploration. We discuss results from floorplan and system primitive exploration across various styles of designs, along with some practical challenges of the ML paradigm.

We all expect our latest mobile devices to have exceptional display performance all within an aggressive power budget to maintain battery life. During a recent GPU project at Samsung Austin, late changing design requirements triggered the need for rapid flow updates to meet the power target. Samsung utilized Cerebrus AI technology to quickly and automatically optimize the implementation full flow to meet demanding PPA goals, and create a Cerebrus ML model, which reduced turnaround time for further flow updates. Attend this session to learn how Samsung Austin successfully taped out a production GPU design, on time, using Cerebrus AI automation.

As MediaTek push power, performance and chip die area of the latest System on Chip (SoC) devices they need to adopt the latest foundry nodes quickly and efficiently.  During a recent move to advance node, Mediatek had to perform new node’s PPA entitlement then further PPA boost by optimizing the complete implementation fullflow and  block floorplans. Rather than spending many months of manual effort, MediaTek deployed Cadence Cerebrus ML optimization to automate the whole process. This leaded to achievements of competitive PPA qualities under demanding project schedule requirements. Attend this session to learn more about how MediaTek improved PPA and engineering team productivity using Cadence Cerebrus ML optimization.

Traditional methods of tuning synthesis and place & route recipes have become increasingly costly to optimize power, performance and area (PPA) in digital designs. The parameters that influence PPA have also increased manifold with the complexities of sub-10nm geometries and significant advancements in EDA tool capabilities in recent years. In this paper, we will discuss the significance of PPA in various phases of project execution and how ML based capabilities can be used to augment traditional workflows. We will discuss Cerberus – ML based optimization flow in detail, and finer integration aspects of the solution in Intel design system and its IT infrastructure. We will also present how Cerberus was used in a production SOC execution context to (i) improve PPA and (ii) accelerate design convergence.  Additionally throw light on future roadmap on how Cerberus when enabled fully on cloud can potentially transform our future design execution and mode of work.

New feature evaluation in RTL requires physical design feedback. Traditionally, floorplanning to enable physical design requires a lot of manual effort.  Especially when it comes to complex IP or SoC, many engineers might work on different features of the same module. This presentation describes a feasibility flow utilizing Genus predict_floorplan feature to generate a floorplan for quick module level synthesis and placement. The flow enables designers to evaluate PPA of new RTL release on any selected modules, which are usually smaller than the physical partitions. Cadence flowtool based YAML flow makes the setup easy to keep pace with the implementation flow. This flow brings in scalability of RTL early evaluation and comparable PPA results with a minimum setup and maintenance effort.

For years, Nvidia, like most companies in semiconductors space, have made use of physical design flows that perform timing optimization in multiple stages. Initially, partition level implementations perform timing optimization within each partition. This is followed by inter-partition and inter-chiplet timing optimization to attain fullchip timing closure. Cadence Tempus has all the necessary tool features to allow development of design flows where partition, inter-partition and inter-chiplet timing optimization can occur simultaneously at each level of design hierarchy. This leads to tremendous improvement in runtime needed for timing closure. Taking advantage of Tempus’ simultaneous hierarchical timing optimization features, fullchip timing closure can be achieved as design partitions are run through the place and route flow. This eliminates the subsequent stages of timing closure, and leads to shorter time-to-tapeout. Additionally, these features also allow development of hierarchical chiplet place and route flows.

Design-technology co-optimization(DTCO) is one of key technologies to keep scaling down chip area in advanced process nodes. One of challenging tasks in DTCO is to secure of the sufficient amount of routing resource under the shrinking the routing resource and increasing complexity of design rule condition. In this work, we propose several design methodologies to overcome the severe design constraints in advanced node such as minimizing the routing usage by using the direct pin connection method with the various pin location. Our experiment demonstrates that additional area scaling can be achieved through the industrial test-cases using the proposed methods.

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, TSV and Micro-bump insertion, extraction, electrothermal analysis, cross-die STA, and inter-die physical verification . A brief introduction to Cadence® Integrity™ 3D-IC platform will be presented which integrates planning, implementation and analysis to address the new requirements of 3D-IC design and signoff for different packaging styles. 

In addition, partitioning a design into multiple chiplets is a significant starting step for multi-chiplet design. For full-stacked 3D designs , it is important to have an automated way to do partitioning, placement, bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and a bottom-up approach for implementation is possible.  In this session, Cadence R&D will present the different approaches to 3D partitioning and  implementation and upcoming features necessary for efficient stacked-die designs.

At lower process nodes, device density increases. And, at high gigahertz frequency, simultaneous switching of densely packed devices can cause sharp fluctuations in voltage, current in power supply network, leading to sharp IR drops and noise. Because this phenomenon can give rise to SI and chip reliability issues, adding decoupling capacitance is a preferred solution. Adding decoupling capacitor can be done using DECAP fillers, however, capacitance formed at very lower layers of process technology such as poly etc that too available at empty spaces not occupied by logic cells effectively leading to lesser than required capacitance values. Therefore, MIM(Metal-Insulator-Metal) capacitance layer insertion can be preferred solution. MIMCAP layers formed between topmost and one below layers of process technology, and this can be put with very high density across whole core region. Previous MIMCAP solution depended on tiled insertion of basic MIMCAP unit cell. And it need to change unit cell layout each time a change in PG grid happens affecting top two layers. Therefore, novel solution needed to address this by putting MIMCAP structure automatically by the tool according to existing PG pattern.

All chips are prone to bugs and these bugs are discovered at different stages of the IC design process. When major development is occurring in the front end phase, these bugs are easily fixed in RTL. But when RTL freeze is done, these bugs should be fixed in Post Route Netlist(PNR). This is referred as Engineering Change Order(ECO). Given the complexity of the design, manually doing an ECO on PNR netlist is difficult and often designers look to EDA tools to automate this task. Cadence Conformal is one such tool that can be used to perform an ECO. In this presentation, we will discuss the flow used to perform ECO using Conformal. We will also look into how existing Conformal LEC flow can be reused to do an ECO.   

In this presentation, we’ll also discuss best known methods for running Conformal-ECO, such as mapping netlist that has multibit flops, using HFEF (Hierarchical Flatten ECO Flow) to reduce runtime on large blocks, planning out synthesis on modules that might expect to be eco (turn off cross-boundary optimization), dealing with Aborts, identify areas that could impact the quality of the eco patches (such as functional map, incomplete constraints to disable DFT, etc.).

Timing constraint (SDC) checking, clock domain crossing (CDC) checks and reset domain crossing (RDC) checks are all essential signoff checks that are crucial for silicon success TI Analog was in the process of transitioning to a new tool for timing constraint checking, CDC and RDC and started using Conformal Constraint Designer (CCD) initially. During this period, we discovered that CCD had some limitations of identifying certain synchronization schemes on our designs which needed a better solution; indeed, a next-generation solution from Cadence had recently become available; Litmus. This paper describes the process of converting to Cadence for SDC/CDC/RDC signoff then upgrading from CCD to Litmus and the collaboration between Cadence and TI on this exciting journey. We dig deep into the inner workings of Litmus as well as share our experience to date and future needs.

As silicon technology advances, designers are constantly pushing the Power-Performance-Area (PPA) envelop. Managing variation and its impact on PPA is one of the foremost challenges in high-performance design. This paper outlines an evolution in STA analysis called Timing Robustness that accurately captures crucial characteristics of process variations and their impact on timing. Through statistical analysis methods, Timing Robustness allows for possible trade-offs between traditional PPA metrics and the overall statistical robustness of the chip which can lead to potentially even greater silicon performance. This paper presents challenges and advances in statistical STA methods, outlines the Timing Robustness approach and provides a demonstration for the adoption of this novel and promising technology.

Accuracy, resolution and throughput are the most important considerations for any scan-based diagnosis method. To identify systematic failures, diagnosis is often performed on thousands of failing devices using automated simulation pipelines.  This methodology, known as volume diagnosis, is a proven approach to accelerate yield learning, but is computationally expensive and sensitive to simulation time and resource availability.

Physically aware logic diagnosis greatly improves callout resolution for some defect types but presents scalability issues for large, complex processor designs.  Incorporating physical layout data into simulations increases resource requirements, complexity, and overhead which significantly reduces throughput.  This presentation highlights challenges and solutions needed to create an efficient high volume physical diagnosis pipeline for IBM 7nm processors in a cloud based environment.  It includes insights derived from statistical analysis of results from thousands of simulations across multiple chip designs.

Key topics addressed: 

1.Background on IBM’s 7nm processors and associated diagnostic challenges

2.High level physically aware diagnosis workflow

3.Maximizing logical to physical correspondence to achieve accurate physical diagnosis results 

4.Scalability enhancements in the Cadence Physical Layout Server

5.Management of Cadence Physical Layout Servers in a cloud environment to minimize resource consumption and overhead

6.Insights on costs and benefits based on analysis of actual high volume results

Embedded systems deployed in safety and mission critical applications are developed to ensure they function correctly and avoid failures by detecting and managing systematic faults and random faults. However, it’s an open question whether these applications are really considered safe with incomplete security architecture. This presentation talks about the need for security in safety applications and touches on the features of Tensilica IP that help develop safe and secure embedded systems in automotive and mission-critical applications.

The CXL ecosystem is rapidly growing while developing design IP, verification IP, protocol analyzers, and test equipment simultaneously.  If issues in products are not discovered until prototype chips are available for interop testing, product and solutions availability for companies and the ecosystem as a whole will be impacted.   Meanwhile, the CXL specifications are advancing to 2.0 and 3.0 revisions, and PCIe is extending to the 6.0 revision, with next-generation products rapidly entering the planning and development stages. To keep up with the torrid pace of design innovations, there is a fundamental change in strategy to massively shift-left the verification of new CXL devices with the host IP.  Intel and Cadence are working together on interop through co-simulation as a key methodology to successfully run complex cache coherent flows and validate interoperability. The CXL simulation interop demonstrates the ability to confidently build host and device IP, while also providing essential feedback to the CXL standards body.

Cadence offers some amazing IP for SoC designs. A great example is the Tensilica Processor IP, a portfolio of configurable and extensible controllers and DSPs. Combined with Cadence’s comprehensive development toolchain, it allows semiconductor companies to quickly create differentiated, domain-specific processors for their application needs. 

However, until recently, there was one thing that those semiconductor companies as well as their end customers were missing out on: Native debug support by the SEGGER J-Link, the most widely used line of debug probes in the market. SEGGER J-Links have provided solid value to embedded development for over 15 years. Unparalleled performance, an extensive feature set, a multitude of supported CPUs, and compatibility with popular development environments all make J-Link an unbeatable choice.

Earlier this year, Cadence and SEGGER started the development of native SEGGER J-Link debug support for Cadence Tensilica processors and DSPs. This means that SEGGER is adding these processors and DSPs to the list of cores that are fully supported by J-Link. In turn, this enables Cadence to use the J-Link GDB Server as a native J-Link driver in their Xtensa Xplorer IDE. 

This presentation highlights how this new native SEGGER J-Link integration into the Cadence Xtensa Xplorer IDE results in a much better experience for engineers developing embedded software for SoCs based on Tensilica Processors and DSPs. Attendees will learn how J-Link’s awareness of these cores lets them take advantage of much higher download and debugging speeds. The session also provides an “under-the-hood” look at the new SEGGER J-Link integration into the Xtensa Xplorer IDE. To round off the presentation, attendees will see a demo of a real-world example of debugging code on a Tensilica DSP using the Xtensa Xplorer IDE and the SEGGER J-Link.

We present an ultra-low power single-rail implementation of Fusion F1 with on-chip SRAM generated by Xenergic’s MemoryTailor. Silicon measurements have shown the F1 sub-system with 512KB SRAM reaches 220MHz at 0.65V with a dynamic power of 19mW. The SRAM used in Fusion F1 DSP was enabled by MemoryTailor, Xenergic’s next-generation memory compiler that automatically optimizes and generates designs for the requested specifications.  Silicon demonstration of the low power DSP sub-system shows that they are ideal for IoT, wakeup domains, and low power Bluetooth applications.

The high-speed I/O data rate keeps pushing for higher speed and the 224Gbps electrical serial link is critical in enabling next generation networking, compute and AI/MI SoCs. What kind of applications require 224G? What are the trade-offs when it comes to different modulation options? This presentation explores possible applications, modulation options and SerDes architectures for next generation 224Gbps electrical interfaces.

System advancements in high-performance computing platforms such as CPUs, GPUs and FPGAs, AI/ML acceleration and high-speed networking are all pushing chip integration to unprecedented levels. Instead of designing these monstrous monolithic chips in a single die, the semiconductor industry is moving to developing smaller and more specialized/optimized dice (chiplets) that can be connected in a single package to provide increased computational power, expanded functionality and improved manufacturing yields.

Enabling high-performance and cost-effective die-to-die (D2D) connectivity requires careful considerations of the D2D interface as large amount of data needs to be delivered over a small die edge under stringent power and latency requirements. In this presentation, we will review the various advanced packaging technologies and  D2D interface options available in the industry, and discuss how to select optimal solutions for specific use cases. Against this backdrop, Cadence UltraLink D2D PHY IP enabled on Samsung advanced process can provide a cost-effective solution for D2D connectivity in these multi-die implementations.

Nearly everybody easily agrees we need "secure" SoCs.Fewer agree what secure SoC entails and even rarely there is a consensus which security functions to implement , how and when. Complicating matters further are application domain specific nuances, provisioning and lifecycle management of security functions of a SoC. This presentation tries to shed some light on the big picture going beyond common misconceptions equating cryptographic primitives with "security" along with a concrete example of implementing Xtensa based secure SoC.

Using DSPs, Hardware accelerators, and AI Engines to process vision, speech, and other sensory inputs efficiently and with low power has proven successful over the past few years. Recently, there has been a growing interest in Ultra Low Power processing for Always-On applications. These applications typically rely traditional signal processing techniques using simple microcontrollers. Throw AI in the mix, and now you have a whole new meaning to Always-On applications. In this presentation, we will highlight the trends and implementations we are seeing in the Always-On market as well as talk about the latest additions to the Cadence Tensilica portfolio to address this market.

Story on how Microsoft is merging multiple independent business unit libraries to one.

I would like to present a brief overview of how the new schematic editor tool from Cadence "Allegro System Capture" is being proliferated at Microsoft ,along with the various custom integrations we built around System Capture that facilitates with other Microsoft's internal tools.

Compared with MIPI D-PHY, MIPI C-PHY does not require a separate clock lane which helps improve EMI issues due to clock signal radiation and provides flexibility so that each lane can work independently 3-phase symbol encoding technology also enables higher data rates at a lower toggling frequency and with smaller number of lanes and pins, further reducing power and cost. According to our product design feature, our PCB design required lengthy routing between the SoC and Camera. In one of our Engineering Development Boards (EDB), we observed SI loss and eye issues. To gauge the design risk and better understand MIPI C-PHY’s practical SI feasibility and performance, we asked Cadence for help and worked with their EDA and SI experts to develop a general and powerful compliance toolkit for MIPI C-PHY simulation. In this presentation we will show how we use this toolkit to investigate system level design layout exploration and optimization for signal integrity using a real IBIS model (not generic) and a real PCB design, including the Common Mode Choke (CMC) effect. We will also show a live demo to familiarize the audience with the tool GUI and usage. We trust that it can easily help others implement MIPI C-PHY designs including SI simulation and compliance checking.

To evaluate the signal integrity performance of high-speed channels, both the dielectric loss and conductor loss needs to be characterized accurately. The dielectric loss is determined by the loss tangent (tanδ) of the dielectric substrates, and the conductor loss is determined by the conductivity and surface roughness of the conductors. The traditional split post dielectric resonator (SPDR) method can be used to characterize tanδ but can only be applied at discrete frequencies and requires metal-free dielectric samples. The traditional surface roughness evaluation technique requires photographing the PCB trace cross-sections, which is time-consuming and requires optical or, in the case of ultrasmooth foils, SEM equipment that is not available in many RF labs. To accurately characterize  tanδ and the conductor’s surface roughness in PCBs a novel  method was proposed which only requires measuring the S-parameters of coupled striplines. By relating modal attenuation factors to the ratio between the differential and common mode per-unit-length resistances, the surface roughness contribution is eliminated and the contributions of dielectric and conductor loss can be separated. No a priori information about the behavior of the dielectric properties or attenuation constant is needed, which allows capture of the arbitrary frequency-dependent behavior of tanδ. After the dielectric loss is determined, the conductor surface roughness is estimated by introducing a surface roughness model and tuning its parameters to match the measured attenuation factor.  This method will allow Cadence Clarity  users to accurately determine PCB parameters from only a few, simple RF measurements.

Cadence Design Systems, Inc. and Dassault Systèmes recently announced (2022) a strategic partnership to provide enterprise customers in multiple vertical markets, including high tech, transportation and mobility, industrial equipment, aerospace and defense, and healthcare, with integrated, next-generation solutions for the development of high performance electronic systems.

The two companies have combined Dassault Systèmes’ 3DEXPERIENCE platform with the Cadence® Allegro® platform in a joint solution that enables companies to master the multidiscipline modeling, simulation and optimization of complex, connected electronic systems. With this new multidisciplinary solution, customers can now accelerate their end-to-end system development process while optimizing their design for performance, reliability, manufacturability, supply resilience, compliance and cost.

Dassault Systèmes and Cadence have been engaged in a multi-year collaboration with leading customers to prove this solution in a global production environment.

The collaborative virtual twin experiences integrate capabilities for electronic and mechanical product lifecycle management, business process analytics and multidiscipline electronic systems development, engineering and traceability. This holistic virtual model provides a complete, real-time view of electrical and mechanical simulation, manufacturing and supply chain execution for the product lifecycle, improving decision-making and accelerating innovation, through “what-if” studies.

Products and services are increasingly interconnected and intelligent, enabling consumers, citizens and patients to unlock more personalized, engaging experiences that improve quality of life. In this dynamic context, companies must rapidly develop electronic systems that are safe, high quality and right the first time. Mastering electronic system complexity and cost/time-to-market pressures requires collaborative innovation that unites electronics, mechanics and additional functions across the value chain.

The presentation will discuss the strategic partnership between Cadence Design Systems, Inc. and Dassault Systèmes that will revolutionize the development of high-performance electronic systems by enabling collaboration around virtual twin experiences.

The push for higher cellular frequencies, greater system integration, and smaller space imparts many unique challenges on RF and packaging engineers in the development of next generation cellular products for 5G, WiFi 6, and other applications. RF engineers need smaller components with higher quality factors and higher self-resonating frequencies (SRF) to address co-existence challenges and higher frequency bands. Packaging engineers need new approaches to integrate these components with system-level devices in an ever-shrinking footprint and package thickness. Many times, these two needs are in conflict with one another. Glass-ceramics have gained a lot of attention as a next generation RF and RF packaging substrate for their ability to simultaneously solve these two important challenges. In this talk 3D Glass Solutions (3DGS) will present on our work using photosensitive glass-ceramics for RF and RF packaging solutions. We will share (1) the advantages of using glass-ceramics versus legacy materials (e.g. ceramics, laminates), (2) applications across a wide frequency range (1GHz – 150GHz), and (3) our simulation experience using Cadence Microwave Office and Clarity in the design of advanced RF filter and packages.

Process design kit (PDK) creation is a large, complex endeavor. Furthermore, the on-going maintenance and upkeep required often leads to PDKs that are lacking or fail to stay current with foundry design rules. At Systems & Processes Engineering Corporation, we have been in the process of developing a broadband PDK for microwave systems-in-a-package design on organic substrates. In this paper we illustrate by example various methods we are using to achieve very complex, broadband, high fidelity designs using Cadence AWR Microwave Office. Several aspects are discussed, including integrated simulation, layout, and process design kit creation. Details of the PDK, including modularity, stackup, synthesis modeling, and thermal management are analyzed. This paper also provides an example of some integrated thin-film filter designs using advanced Microwave Office features including iFilter, optimization, closed form solution, and Axiem EM synthesis. A comparison between filter simulation and measured data is also given. We have leveraged the Script Development Environment within Microwave Office to create a series of scripts to assist with project and project library management. Initially conceived as a suite of scripts for various individual project library maintenance tasks, has led to a full-fledged user tool we use to analyze and compare our in-development AWR project library with a backup repository of DXF drawings to maintain consistency and cohesion between the active project and the backup.

In this presentation we provide a quick overview of several exciting Earth and planetary science investigations that are performed by JPL and NASA from UHF to Terahertz wavelengths and addressed by chipsets developed using a wide range of Cadence EDA tools (primarily the Spectre simulator). We will discuss the important role CMOS system-on-chip (SoC) technology plays in spaceborne science instruments, and the fundamental design challenges that these SoCs face in delivering the level of fidelity required for NASA’s science investigations. 

Four recent CMOS SoC based instruments developed with Cadence Spectre and Innovus for upcoming NASA missions will be presented. First, the NASA WHATSUP 600 GHz emission spectrometer which measures isotopic ratios of water at Europa, Titan, and Enceladus to better understand the origins of water in our solar system. Second, an all-digital ground penetrating radar for the Mars Science Helicopter that explores subsurface deposits of ice at the Martian poles to be better understand the origins of water and ice on the red planet. Third, the NASA EMTS mission monitoring the snowpack water content in the southwestern united states to provide states accurate water resource planning during periods of prolonged drought. Lastly, the NASA SpecChip instrument which explores comets and asteroids, analyzing the gassed trapped within their icy surfaces when the solar system first formed, and giving us a glimpse into our cosmic origins.

 

Management of localized heating in ICs at the transistor level is important for avoiding temperature-related problems ranging from skewed device functionality, lifetime reduction, or even catastrophic failure. An alternative to using simplistic or empirical methods for estimating heat flow was needed to reduce uncertainty and wasted iterations for new layout and circuit designs, as well as enable wafer foundry customers to, themselves, design aggressively, taking specific packaging and other off-chip thermal factors into account.

Cadence AE’s worked with Tower to demonstrate the use of Celsius in calculating junction temperatures for various designs in our process nodes, both in the context of wafer-level testing and at the packaged component level. Built-in Celsius templates and functions were used to import and analyze test chip layouts, building realistic and comprehensive 3D thermal models that incorporated material geometry and thermal property effects such as technology cross section, die size, back-grind thickness, package type, and PCB configurations. Standard workflows were used to specify the heat sources and ambient conditions and manage simulations. Results of interest included solving the temperature distribution in power transistor arrays, their bias limitations imposed by thermal runaway, the effect of deep trench isolation, and the heating of components on insulating substrates, culminating in our determination that a key reference design's rated performance would not be limited by excessive junction temperature.

The design effort for upcoming integrated circuit and package technologies is rising because of increasing complexity. To achieve required specification values with a good trade-off of system size, current consumption, performance and costs, it is necessary to have a design flow, that enable comprehensive optimization across all components of a system. This presentation covers a system consisting of an IC manufactured in a SOI technology and an advanced packaging substrate. Both designs have been implemented within Cadence tooling. In this case Cadence Virtuoso is used for the IC and Cadence Allegro is used for the package design. To enable shifting of components from IC to package or vice versa, a tool flow was used, that enables annotation between both design tools. Using analysis tools like EMX or Clarity different variants of implementation across IC and package have been investigated and been analyzed to choose for the best solution. The system is currently in production and the presentation will also cover measurement results as well as an comparison of the simulation and measurement results.

The Chemical Mechanical Polishing (CMP) variation on a die depends on the die’s location on the wafer. For example, the post CMP thickness and/or topography variation on the center die can be very different from those on the mid-radius and edge dies. Consequently, the number of CMP hotspots and the hotspot locations can vary from die to die on a wafer. Most CMP simulation tools focus primarily on predicting the CMP effects/performance on a single die on the patterned wafer, and do not have wafer level prediction capabilities. <multiple dies for one product – wafer level simulation importance, wafer level bonding > In order for CMP simulation to be more widely used in process development and optimization, and in yield prediction and optimization, CMP simulation tools should be able to predict the CMP performance across the entire wafer.

In this paper, we present and analyze CMP data from multiple dies on BEOL Cu interconnect levels and show the wafer level effects in the polishing process. We also show wafer level modeling results for the polishing process using Cadence’s CMP simulator. We make use of an automated profile scan plotting utility in comparing and analyzing the profile scans from different dies on the wafer.

The industry has not had many new structures in the last sixty years.  Multilayers have continued to evolve with thinner materials, smaller traces / spaces as well as drilled vias.  It’s been nearly forty years since the first laser-drilled microvia boards went into production.

Microslotting is a true 3D concept for interconnection by creating a routing channel (slot) in the printed circuit that then can be metallized and plated easier than microvias and allows connection to innerlayers.  This allows HDI densities higher electrical performance and reliability.

System on Chip (SoC) Architects consider design decisions based on requirements from the software developers that will target their processor-based products. Architects must consider workload-specific requirements from real-time signal processing, security & trusted firmware, to sophisticated AI/ML algorithms early in the design cycle. Thanks to flexible IP subscriptions programs, there are more options to consider than ever. Understanding differences between available compute IP Building Blocks typically involves detailed specification review and multiple meetings with IP vendors to match IP solutions to requirements. Selecting the right CPU for the given software requirements and optimizing the IP configuration has traditionally involved intensive R&D activities that range from modeling and prototyping, porting software, and benchmarking - requiring up-front investment in development tools, compute infrastructure, and months of engineering resources.

This presentation will introduce a cloud-based SoC development methodology that simplifies the front-end design process. We will demonstrate how the SoC architect can discover and compare options curated to meet their industry-specific product goals - saving weeks of ramp-up. We will show how on-demand IP selection services allow users to save months of IP evaluation by simulating exactly how the recommended IP solution will perform when running industry-standard software and benchmarks, or & even custom algorithms.

We will also discuss potential pathways towards connecting the early IP selection and configuration process with cloud-based verification of the actual SoC.

An industry-wide problem that is sometimes encountered when integrating RTL developed by different teams is that the same names may be used, when the content those names represent may be very different. Traditionally either 1) a single definition is used throughout the resulting design, 2) the colliding modules are uniquified to remove the collision, or 3) v2k configurations are used to map each definition to the intended hierarchy. Each of these solutions does work, but in some cases these methods delay integration and involve a measure of risk as well – risk that a collision goes silently unnoticed. Various tool features exist which together can aid in helping ensure that content within the same library is preferred over content from another library, reducing the need to use the more extreme traditional methods for handling such collisions – even when the collisions cross RTL language boundaries.

Want to decrease your verification time by 100x? Together with Arm Fast Models, Cadence’s Helium Studio runs up to 100 times faster in hybrid mode, giving the end user a substantial reduction in verification time and improving overall time to market. In this talk we’ll focus on a 5G design use case involving Layer 2 and Layer 3 protocol software and show how verification time was significantly shortened for an Arm-based design using hybrid mode. With the CPU subsystem running on the virtual side connected via Cadence’s Accelerated Verification IP to the interconnect, phy, memory controller and DDR on Palladium, the entire system under test runs orders of magnitude faster than pure RTL in emulation. Join this session to see how it’s done.

The demand for network capacity is increasing thanks to cloud computing, mobile edge computing, and 5G technology. Network equipment and semiconductor manufacturers need to keep up with this change by delivering ultra-high-density devices powered by cutting-edge application-specific integrated circuit (ASIC) and system-on-a-chip (SoC) solutions. To achieve aggressive time-to-market and cost-efficiency requirements, post-silicon validations are no longer sufficient. Design issues found late in post-silicon validation can cost a thousand hours of wasted effort. In addition, today’s climate will no longer support waiting until the design is baked into silicon to thoroughly validate chips. Semiconductor manufacturers need to migrate away from hardware solutions for pre-silicon verification and post-silicon validation. 

To overcome these limitations, it’s time to complete silicon emulation at the Layer 1 level, and eventually, beyond. When a chipset’s entire design can be emulated, testing and bug fixes can happen in real-time. Beyond that, automation is the key to success. A testing ecosystem has been built to include pre- and post-silicon validation of physical or virtualized infrastructure and fully automated testbeds to maintain CI/CD integrity. With a simplified testbed powered by automation, testing teams do not need to learn different scripts or write million lines of code. Also, as Electronic Design Automation (EDA) emulation and testing are becoming virtual, pre-silicon testing solutions are evolving. Instead of being constrained by limited pre-purchased test ports, virtualized testing supports the scale and automated workflows required to quickly test thousand ports and easily modify the functional building blocks under test. It provides the agility and power to emulate a variety of protocols and traffic situations. 

This presentation describes how Spirent Communications is partnering with Cadence to integrate automated test emulation into Cadence’s solution and to make end-to-end silicon testing, support, and services a reality. The testing solution helps customers to verify chipset design early in development cycle. The solution integrates STCv (Spirent Tester Center Virtual) L2-3 traffic generator with Cadence Virtual Network Tester Solution (Palladium Hardware Emulator). This presentation also shows how this joint solution saves costs, bridges gaps between pre- and post-silicon verification, delivers significant benefits to customers, and accelerates time-to-market.

For top level design verification, analog blocks are usually the bottleneck of the simulation performance. In order to speed up the simulation, various of modeling techniques have been used for analog blocks. Sometimes it means a trade off between accuracy and performance. 

Real Number Modeling (RNM) using SystemVerilog real ports is very useful for analog modeling, it simulates the top level testbench with pure digital simulator and keep the accuracy of the signals. However, there are often some number of nodes in a system that can’t be simply modeled by just a voltage or a current. These are the points where there is some level of impedance dependent interaction occurring between modules at a high enough level that it needs to be implemented for proper operation of the system level verification runs. This is exactly the point where a UDN such as EEnet can be used to effectively model the actual interaction. 

A case study of top-level simulation in the Digital-on-Top environment with EEnet models is presented. These “EEnets” model voltage, current, and source resistance of the testbench drivers. The same stimulus generated for DMS simulations which use EEnets for the device pins with multiple drivers is shared for AMS simulation. Custom EEnet connect modules are added for AMS simulation. 

In order to probe current on EEnet ports, a new Cadence methodology to register attributes (properties) of the IP blocks is applied in the case study design as a part of the IP creation process. Once registered, the properties are available to create probes on for viewing in debugger (waveform viewer) and can be accessed universally anywhere in the testbench. This will allow both Testbench and IP to become portable. Build and run time may increase drastically when RNM models with EEnet is brought in. SV-UDN profiling technology for Xcelium mixed signal sims from Cadence is piloted to help performance debug. 

Proposed takeaways: modeling the analog behavior with EEnet makes it possible to do the design verification in a pure digital world which is much faster while still keeping the good accuracy as in the analog world by bring in the impedance for consideration. A methodology to register attributes of the IP blocks makes IP portable and reusable.

The complexity of designs increases with each generation, while time-to-market schedules tighten. 

Using the common methodology for Emulation and Prototyping, users are able to optimize workload distribution between verification, validation and pre-silicon software bring-up. 

In this presentation you will learn the benefits of a common methodology, Hardware debug tools on emulation and Software debug tools on prototyping that will accelerate your pre-silicon product development process and optimize your shift-left strategy.

Problem Statement: Multiple tools and methodologies are in place for different DV activities across projects and teams. For example, Jasper CSR for MMR (Memory Map Register) verification, CONN for connectivity checks, FPV for assertions checks, generate coverage data to monitor progress in vManager or vPlanner etc. This in turn has an impact on overall execution, cycle time and resources. The proposed solution extends the basic capabilities of Jasper CSR to achieve more than just MMR verification. Prior Art:Most teams use Jasper CSR only for MMR verification. This in itself is a strong methodology but it is not a complete check. Depending upon how MMRs are spread across in the design, for example all MMRs in one file vs IP specific MMRs in each IP block, the usage of CSR changes. This also leads to gaps in methodology where DV needs to be done not only on MMR write and read, but also on connectivity of each bits. Proposed Solution:This paper describes a methodology that resolved this issue by developing a flow which automates the generation of all required CSR inputs with minimal additional effort from design teams. The flow enhances register map verification to check for signals and registers at different level of hierarchy. This enables checking the connectivity of these signals with associated register bits across different levels of design hierarchy. A methodology has been proposed to find signals using the address bus reducing debug time for verification engineers. The flow also enables register access types not readily available by Jasper CSR. The flow makes good use of coverage data achieved by CSR properties with the COV app.

At NVIDIA, in addition to the HW/RTL verification, we strive to complete the full SW checkout before the chip tapes out. There are major challenges in achieving this goal in Emulation late availability of some of the IPs including CPU, a huge number of SW testplans that involve various teams and use cases, and the significant amount of time it takes to execute these testplans even on a perfect RTL. Helium Hybrid platform provided us a way to work around these limitations and we have used the platform on both Palladium and Protium to enable our SW teams to bring-up the Kernel and the required software/drivers to successfully verify other IPs at SoC level. Our goal was to enable the verification of various IPs at SoC level. It’s not uncommon for CPU RTL to be not ready for Emulation while other critical IPs are available for HW/SW verification. We have used the Helium Virtual and Hybrid Studio to build out a hybrid platform combining virtual platform level models of CPU cores and few IP blocks that were still under development with RTL for the units that were ready and available for verification. The Kernel boot on this platform was substantially faster resulting in quicker bring-up and execution of various testplans. While we do emulate these late arriving units when they become available from HW verification perspective, we have primarily used the hybrid platform for SW checkout due to its substantial throughput advantage. The ability to save and restore a session both on the Virtual as well as Emulator sides provided greater flexibility in the execution of various testplans in different use cases. One key value was the ability to seamlessly transition our hybrid and test environments between Palladium and Protium. This capability enabled maximizing the value of our hardware investment. Essentially the ease of transition of the hybrid helped us realize the value of the Dynamic Duo. An unexpected value came from the runtime configurability of the design as delivered to the software users. We now build configurability into our platform and simply train our software users to make session specific changes through parameter changes. The result is that we can generally produce a single build of any given netlist while the software and verification users can easily move between target software loads by changing parameters. Our users also got substantial value out of the Helium tools above and beyond the simple value of performance provided by the hybrid. The fully featured interactive software debugger with a unified view of all system state provided the expected value for kernel and driver debug. Additionally, our users found the ability to validate and debug the embedded C test cases very useful. This was not only used in the Hybrid, but also in a pure virtual setup to debug tests prior to putting them on the RTL so that we could debug the test in a known good environment.

DFT simulations are among the longest simulations to run and tend to occur at the end of an ASIC project. They tend to run for hours, days, and even weeks because there are a very large number of tests and those tests activate most of the design. In general, event simulators slow down as the event-density, events per simulation time step, grows. DFT simulations have this characteristic. When ECOs force a rerun of these DFT simulations it can impact the tape-out schedule. Xcelium Multi-Core alleviates this issue by distributing those simulation events among multiple cores enabling faster simulation. This presentation will describe this situation in more detail and show how Lightelligence applied Xcelium Multi-Core with no change to its DFT simulation set-up to achieve up to 3X speed-up.

Speeding the deployment of A&D systems is increasingly dependent on fast, assured development. BAE Space Systems develops processors that have flown billions of miles throughout the solar system.  Customers add software and integrate those processors into spacecraft using prototypes developed by BAE Space Systems.  The first step toward a more efficient prototyping flow was to apply the Cadence Palladium system to verifying hardware in the context of software the results of which were reported at Cadence Connect Boston in October 2020.  The next step was to explore how the Cadence Protium system could be used to reduce the time to bring-up a prototype and model how a customer’s software engineer would work with that prototype.  During the second half of 2021 BAE demonstrated that Protium did reduce the time to bring-up the prototype and provided a good environment in which to verify software.  This presentation will report on this process and the results from the perspective of a software engineer.