Cadence Tensilica Vision DSP系列产品是在业界公认的图像处理，视觉处理及AI处理的最佳选择。在这个研讨会上，我们会和大家一起分享下市场的趋势以及对Vision DSP提出需求的应用。然后，我们将向大家介绍1款新发布的产品 Vision P1,针对对功耗极其敏感的CV和AI的应用。

Cadence Tensilica将介绍一个新DSP系列。此次主题演讲是了解新产品的极佳机会。更多细节，敬请期待。

本文基于Cadence的Virtuoso RF Solution Cross Fabric流程与Clarity工具，可以方便的实现上述DIE与Package的Co-Simulation。Virtuoso RF Solution Cross Fabric流程配合Clarity工具，可以基于DIE与Package原本在分立平台的设计文件，由软件来完成从文件整合、文件提取到仿真的全流程。将DIE与Package视为一体进行分析，实现DIE内部节点到Package的Ball管脚乃至PCB板的信号完整性3D电磁场仿真。避免了DIE与Package单独仿真造成的接口部分仿真缺失或者接口部分仿真设置复杂/不合理导致的结果不可信，提高了TO前验证的充分性和准确度。

本文将结合实际项目，讨论Virtuoso RF Solution Cross Fabric仿真流程的有效性、操作的方便程度以及仿真的时效性。

Cadence EMX 平面 3D 仿真器是用于高频、RF 和混合信号集成电路的大规模平面3D电磁电磁仿真器。它可以准确、高效地仿真大规模 RF 电路模块，描述无源器件行为并分析由互联引入的寄生效应。当今射频系统的设计常常需要用到多种工具，Cadence Virtuoso RF解决方案处理了这个极具挑战的问题，它将这些工具集成在一个统一的环境和流程中。将EM引擎集成到Electromagnetic Solver Assistant中，可使 EM 提取和分析完全自动化且省时。用户可以通过这一个接口创建模型、生成 RF 数据，并将其保存为可以直接运行仿真的数据。EMX便是这些EM仿真引擎中其中的一种。本文将结合实际项目展示如何在VRF流程中使用EMX，通过对比可看出其相对传统EMX使用方式的优势。

本文将讨论如何优化并利用矩信息，以提高先进制程偏差中标准单元库的时序信息的准确性、有效性和可行性。此外，本文还会深入探讨在LVF中引入更高阶矩的可能性，提高OCV信息产出的效率和价值，故而提高STA结果的可靠性，保证芯片产出高良率。

本文分为五大内容，首先描述矩在数学和统计学中的概念，而后讨论标准单元库工艺偏差的表征，及先进工艺的表征标准；在第四部分，通过使用Cadence Spectre和Liberate进行先进工艺标准单元库Liberty文件的矩信息萃取，通过实例数据和图表具体剖析如何优化和利用LVF中的矩信息；最后，我们将探讨引入更高阶矩的可能性。

This slide will firstly describe the overview of electrical view creation flow of analog & mixed signal circuits including characterization, partition and library creation. Then it will tell what information will be extracted from the target circuits through the Cadence characterization tool - Liberate_AMS, and finally the concrete steps that the liberate_AMS will execute in a characterization part. Then an example of how to characterize an analog circuit with Liberate_AMS will be given. The target application is a gephy analog circuit in FinFET, as FinFET process has been widely proposed. The circuits should be simplified and extracted to the extent the circuit structure information will not lose, and also the simulation speed can be guaranteed.

For top level mixed signal design verification, locating the source of abnormal current consumption is difficult and tedious. SimVisionMS, a new digital/mixed-signal simulation cockpit integrated in SimVision, is targeted to the TI needs and presented as a novel solution. With this solution, terminal currents can be viewed interactively and traced down to the leaf level of every node; Verilog-AMS/Spectre/SPICE text contents will be shown in Schematic Tracer as schematics, which allows to review connectivity and current distribution easily; Spectre and SPICE source file can be cross probed in the Source Browser.

Cadence的ADE Verifier工具是基于Virtuoso的项目管理平台，适用于需求驱动的模拟设计验证管理，可以对不同designer设计的不同子模块进行统一管理和验证，可以对芯片各个子模块基于Virtuoso ADE Assembler以及Explorer的仿真进行整合。

本文基于我方的实际项目讨论了Cadence的ADE Verifier工具对上述需求的支撑。可较好地提升芯片设计过程中，对项目进行验证和管理的工作效率，并降低为此而投入的人力成本。

Success in today's electronics market place,Most SoCs currently being developed have analog or mixed signal blocks, many so-called analog blocks actually have digital-control logic A.Virtuoso-Innovus flow with MS OpenAccess RapidPDK allows for all or parts of the physical hierarchy to pass back and forth between Virtuoso and Innovus technologies easily without having to generate a DEF/GDS file. In this paper, we first describe the way to generate 5nm Rapid PDK, then use this pdk with digital flow to finish 5nm IP design with custom lib. Additionally, this virtuoso-innovus flow provides our analog designers with advanced techniques for 5nm floorplanning, pin optimization, track generation and auto place & routing with RC extraction and timing analysis aware which will simplifies the flow to enable Virtuoso users to run 5nm layout implementation, and also could help us to do full chip STA analysis

Cadence于2019年推出APS的下一代模拟全精度仿真器Spectre X，在实际使用过程中发现其对普通模拟仿真性能提升明显并且基本保持了APS的仿真精度。2020年，Cadence推出其APS RF的下一代仿真器Spectre X RF 仿真器。RF仿真在我们整体仿真验证流程中同样占据很大一部分， 在将其应用到实际项目前， 需要与APS RF对比其性能和速度。

这篇文章主要介绍了Spectre X RF的用法，并重点介绍在几种采用不同工艺的RFIC设计中， 仿真器Spectre APS RF与Spectre X RF 仿真性能与精度的对比情况。

When we use traditional timing signoff (STA) with a proper margin or derate for voltage variations, it will help us to cover most scenarios of real silicon. But as chips are designed larger and larger, features of hardware and software increase more and more, we see some critical cases will lead timing to fail caused by IR drop, even if IR analysis is under criteria. Now, most of our designs such as AI chips are designed on 12nm, 7nm or less, with a 3DIC interposer.  IR drop analysis is more and more complex and important. Meanwhile, timing analysis with IR drop requests. Tempus Power Integrity provides a true signoff solution for concurrent IR drop and timing, which helps us find the real critical timing path with voltage-sensitive.

This paper introduces Stylus Genus iSpatial flow implementation on 54 million gatecounts, 28nm FDSOI, Arm core design. First, iSpatial flow and Stylus flow are introduced. Stylus iSpatial flow provides unified and predictable flow from synthesis to PR in common user interface and consistent setup&report. Then, Stylus Genus iSpatial flow building method is proposed. After proper setup, new flow is run and compared to original flow. By iSpatial engine, synthesis does most place optimization job with better PPA, then data passes down to Innovus seamlessly for place incremental optimization and following steps in Stylus platform. At last, summary result is given between iSpatial flow and regular flow.

In this paper, it is illustrated that with all the powerful FIP and SRAM listed above, ARM Cortex A75 cores are implemented successfully using Cadence Stylus flow (Genus for synthesis, Innovus for place and route, Voltus for power signoff and Tempus for timing signoff). During the implementation stage, several powerful techniques that Innovus supports help improve overall QoR impressively.

Our chip is a NPU SOC with more than 400 million instances, hundreds of soft blocks, more than ten thousand macros, thousands of clocks and the chip area is more than 600 mm2 using TSMC 16nm technology which all give big challenge to the EDA tools and design resources. In this paper, we will share what we do with Genus i-spatial flow, Innovus i-spatial flow and our customized synthesis flow.

Genus i-spatial gives better correlation and acceptable run-time than our former flow, result in a good QoR in PR stage. In addition, during the early stage of the project, with Innovus mix-placer flow, we successfully achieved accurate evaluation without the participation of physical design team, saves our working resources.

在7/5nm工艺下instance呈现翻倍增长，同时面临更高性能和数据吞吐量的需求，传统的EDA Flow不太容易满足后端设计要求。通过Mixed Placement,在项目初期没有Floorplan的条件下时，在Genus 中通过predict_floorplan 调用Innovus 快速做一次Mixed Placement，生成一个Floorplan 出来。在设计早期就可以进行iSpatial流程，可以及早的发现设计的Congestion 问题，而且可以提前预测preCTS阶段时序，便于更早的进行代码优化。

• Challenge of Large Scale Design: Capacity/Runtime/resource/PPA Challenge

• Strategy for block level Synthesis: Synthesis criteria for different strategy, Alchip block level synthesis strategy

• Hierarchical Synthesis Flow: ETM flow VS ILM flow, Alchip Hierarchical flow

At the advanced process nodes, the increase number of operating modes and process-voltage-temperature(PVT) corners brought the increase of signoff mode, which makes final timing closure is fast becoming the bottleneck of tapeout. In response to this question, the use of signoffOptDesign(SOD) convergence method, directly in-design fix based on signoff results by invoke Qrc and Tempus tools, compared with traditional convergence method, can be effective reduce the turn-around time(TAT), thereby accelerating the the overall convergence of the design. In actual projects, through comparing the traditional timing convergence method and SOD timing convergence method, it is found that the timing convergence using SOD can reach almost a consistent result with lesser TAT required by the traditional convergence method, which effectively reduces the overall design convergence interval.

This paper proposes “track-based power stripe design” to achieve best routing track utilization for power stripes. First, power stripe “on-track” conception is introduced -- When regular wire is routed legally on neighbouring track, there’s no space waste between power stripe and regular net. For “on-track” power stripe, it should have both specific width and correct location, otherwise, there’s either “track-waste” or “width-waste”. Then in Innovus, one procedure is developed to check all power stripes. Problematic stripes are highlighted for review and optimization. After that, several chips/submodules are checked as example. With “track-based power stripe” re-design, hundreds to thousands routing tracks can be saved without punishment of total stripe width.

Next, one further topic is discussed. For each layer, if total stripe width is not changed, which stripes width can achieve high routing-track efficiency and which stripe width can achieve best efficiency? Analysis is done and result shows piecewise relationship because of wide metal space rule. Result table is first-hand guideline to design high efficient power stripe, but in real case, more factors especially IR drop should be co-considered to decide final stripe strategy.

At last, “track-based power stripe design” methodology is summarized.

With the help of Cadence's newly IR Aware Full Flow, the author uses local P/G stripe addition, timing aware IR drop fixing, IR aware placement etc. to avoid and address IR drop issues all through the PR flow. These techniques significantly improve the efficiency of IR drop hot spot fixing and greatly accelerate the convergence of IR drop problems. IR Aware Full Flow saves designers much more time in getting a better PPA result and is of great use to the design process of IC physical implementation.

With CMOS feature size scaling, the increased chip density and the operating frequency have made the power consumption a great concern in VLSI design. The power cost can be classified as dynamic and leakage (static) power consumption. As the contributor to the dynamic power, a glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay at the inputs of a gate is greater than inertial delay, which results in notable amount of power consumption, especially for designs with deep logic levels. In this work, based on our library study results by using the Cadence tool Joules, we found that adopting the adaptive body bias (ABB) technology can have great glitch suppression without performance degradation, which have been demonstrated by two cases implemented by Cadence Innovus with GF 22nm FDSOI technology. It is suggested that more than 30% glitch power can be reduced compared with the zero body bias (ZBB) mode. Additionally, from the Cadence Voltus results, the serious dynamic IR drop due to the high activity induced by the glitch can also be relaxed obviously.

随着系统功能的日益复杂和速率快速提升，对于PCB的通流压力越来越大，常规的评估通流能力方式遇到了瓶颈，不能满足产品日益增加的电流需求。需要探索一种新的仿真评估方法，通过电热联合仿真来准确评估由于PCB引起的温升，并借助系统散热边界条件来提升通流能力是一种可行的方式，本文基于Power dc 进行了大量的仿测对比工作，验证了仿真方法工具的精确程度，并利于热交换系数成功导入系统边界条件，极大的提升了PCB的通流能力。

随着云计算，云数据中心以及5G带来的数据传输量和速率的不断攀升，高带宽，低功耗并行接口将逐渐成为大型数据传输和运算的关键接口。超高的速率给整个DDR通道，包括并不限于芯片，封装基板、PCB和连接器的设计和仿真带来了挑战。本议题将讨论6400Mbps LPDDR5高速通道设计带来的新挑战以及应对方式，并讨论如何使用Cadence® Sigrity™技术和Cadence® Clarity™ 3D Solver来解决这些挑战。

Allegro PCB Symphony Team Design-Cadence推出的多人协同功能，支持多人协作布局、设规则、布线和交互式联合审查。复杂，高速的PCB，而相差无几的周期对于不同的工程师团队协作提出很高要求。Symphony可以确保团队高效运作，灵活地配置专业工程师资源，使不同的功能和不同经验的工程师实时、并行在同一设计中协作，完成PCB板设计和检查，极大地节省PCB设计周期，加速产品上市。

DFM means Design For manufacturability which is executed by Manufacturing site to review if the PCB design can meet the requirements for mass production according to some manufacturing rules, but doing DFM check in PCB design phase can help PCB designer mitigate some violations of manufacturing rules before submission to Manufacturing site, which can improve efficiency, save time for PCB to PCBA end to end and avoid cost waste during the whole process. The topic is to introduce how DFM works in Cadence.

Cadence® Allegro™提供了一个基于Multi-zones的刚柔结合板设计平台，在Allegro工具中，我们可以轻松地在一个设计文件中完成刚柔结合板的设计。而在Cadence® Clarity™3D Solver中，我们可以直接将Allegro完成的刚柔结合板设计导入，无需进行额外的结构编辑，并进行整板的三维全波电磁仿真，从而避免了对设计的切割及后期S参数结果的级联，在充分考虑刚板和柔板之间的耦合及阻抗不连续性的情况下，快速得到了高精度的仿真结果。借助Allegro和Clarity完整而成熟的设计和仿真流程，我们得以快速高效地完成刚柔结合板的设计和EM性能签核。

This presentation developed a novel methodology to design and qualify HBM memory system performance to meet JEDEC standards based on solid SI/PI simulation technology with complete consideration of Simultaneously Switching Noise(SSN) effects on such massive parallel I/O performance. Also, technical simulation results have been rigorously verified with Lab measurement to proven the simulation technology’s capability can meet our production requirement.

Virtuoso RF解决方案是一种基于Virtuoso平台的系统感知设计解决方案。借助VRF流程，我们可以轻松地将PKG物理设计导入到Virtuoso中，并将合并了IC和PKG的设计调用Clarity 3D Solver用于电磁（EM）分析。 Cadence®Clarity™3D解算器是一种全波三维电磁（EM）仿真软件工具，用于设计IC，封装，PCB，系统及其不同组合的关键互连。我们在Clarity中合并了IC部分和PKG部分，并进行了EM协同仿真，从而获得了IC和PKG之间的耦合干扰，精度很高。借助Clarity生成的S参数模型，我们可以实现系统感知的仿真，并在流片之前对关键规格进行良好的评估。

In this paper, we will test the real channel performance after calibration, and use the Sigrity clarity 3D to simulate and fit it, observe the simulation accuracy and efficiency, and give the actual case suggestions.

As SoC is becoming more and more complex,  the SoC low-power design has more and more power domains and power states which brings a big challenge to the SoC low-power functions for a qualified verification . This paper focus on the dynamic verification for the low-power functions. To verify the low-power functions completely,  it’s necessary to active the power-on devices under test (DUT) randomly when changing the low-power states randomly in one pattern with complete checkers and coverage. This paper would introduce a complete scalable solution and platform for the complex low-power verification with little effort.

This paper elaborates the common basic flow used in Qualcomm SOC projects, from register automatic flow,  coherence issues, and performance scenarios.  With simple registers’ description files and Project configuration tables and SOC test configuration tables which design intent are captured, tests can be generated even before RTL is ready. The advantage of reuse and efficiency is so obvious, Verification engineers just need to update these chips' tables according to new projects or some of low level drivers, tests can be generated automatically,  It reduces times engineers take to create tests by manual no mater with C or SV cases,  With thorough abstract and system level design intents been captured and reviewed across teams, bugs can be found at earlier stages,  with randomized scenario generation scheme,  all possible corners can be targeted efficiently.  Along with Cadence Perspec which fully supports the PSS released by Accellera, scripts for pre and post-processing are also required as a complete methodology.

• Introduction
• FPGA Prototyping Challenges
• Palladium Z1+ Protium X1 co-verification Solution
• Results
• Summary

对于800G以太网的验证，目前存在2个痛点：1）800G并没有成为IEEE的标准，目前仍处于草案讨论阶段，需要与第三方对接验证协议理解一致性；2）芯片size的快速增长会拖慢软件仿真的效率，增加迭代周期。

针对痛点问题，Palladium加速器以及配套的以太网Speedbridge能够快速bringup仿真环境，实现设计代码与第三方代码的对接测试。满足芯片的功能以及性能验证，验证效率提高数十倍的同时，还能够在流片前开展软硬件联合仿真，对缩短项目周期起到实质性帮助。以太网Speedbridge支持10M至800G等全部常见以太网速率，并且支持xMII和PCS两种接口与待测设计对接，支持PCS接口位宽，lane数量的定制化服务。

本文介绍了验证管理工具vManager，通过python调用vAPI接口与企业级的产品需求管理系统Microsoft TFS和用户数据后台对接 ， 实现了从自动创建验证需求框架（即vPlan）, 自动执行回归验证，自动提取验证结果反标Microsoft TFS中的需求状态，自动提取验证结果呈现到验证看板的自动化验证管理全流程。本方案旨在自动化、规范化地实现验证需求到vPlan的同步，验证回归状态和覆盖率数据的实时汇总，实现验证的高效率与高透明度，需求跟踪达到滴水不漏。该方案还采用了vManager最新一代的High Available模式，可实现跨地域的多团队合作与数据共享，并部署了多引擎验证工具的包括Xcelium, JasperGold和Palladium的验证管理，实现多维度的验证数据汇总。目前该方案已经部署真实研发环境中，为vManager在国内比较领先的应用，为业内提供跨地域合作+多个仿真引擎的大规模自动化验证方案提供非常有价值的参考。

ARM CHINA, the leader of IP supplies, is keep working on releasing IP product with more functions and efficiency, which takes us great effort in IP design verification. With the help of Indago, a debug tool from Cadence, verification engineers are able to locate and resolve issues during debugging. Indago supports several levels of debug mode for users with different application situations. Engineers are able to do waveform review, design circuit inspect, low power states and even proceed offline breakpoint debug after simulation. We will present the experiences of Indago practical application in presentation.

Our company has developed a set of scenarios for verifying MIPI or using MIPI to verify internal image processing modules based on MIPI AVIP, which has achieved dozens of times of acceleration ratio and greatly improved the simulation speed. As well as using AMBA AVIP to simulate and monitor the behavior of related modules which can be used to get the pre-netlist power data and performance data .It has made an important contribution to the functional verification and power/performance optimization of the chip.