With the rapid growth in design complexity and demands of leading process nodes, the compute and infrastructure needs for next-generation designs pose new, daunting challenges. That’s why every high-performance team is looking at Cloud with great interest. The scalability and agility offered by cloud addresses many of the gaps in design infrastructure. However, transitioning to cloud requires thoughtful decisions about cloud architecture, data management, infrastructure setup, security, to name a few. In this session, we will discuss the pros and cons of various cloud architectures, their suitability for design flows and IT needs for successful cloud transition. We will also describe the Cadence Cloud solutions used by over 100 customers to successfully embrace cloud for their production designs.

The connected world is a big business, and semiconductors are the underpinnings of every industry segment—from communications, computing, and automotive to the Internet of Things (IoT) and media and entertainment. The insatiable demand for semiconductors has pushed global revenues past the $450 billion mark.
These trends—demand, speed, complexity, and agility—call for a reassessment of how silicon design is done from a toolchain and infrastructure perspective.
Microsoft is working to improve the complex electronic design automation (EDA) software landscape, boost productivity, optimize resources, and speed up time to market. We work closely with foundry partners and EDA vendors to develop finely tuned solutions that run on Azure High Performance Computing (HPC) infrastructures.
In this 60mins session, we will brief you from the latest case studies with Cadence, how does Microsoft Azure not only streamline the process, but also cut down Total Cost of Ownership while optimize the runtime under purpose- built architecture.

AWS semiconductor design customers can quickly launch a secure IC/SOC development environment, allowing teams from small and large fabless semiconductor companies, and their external collaborators, to reduce time to market and speed the semiconductor development process. In this presentation we will guide you through the process of scaling out your workflows on AWS, from RTL to Silicon. With a step by step walk through of an AWS reference architecture diagram, we'll provide guidance for connections, infrastructure for the design environment, data transfer, data analytics, and how to enable collaboration across the semiconductor ecosystem. Additionally, we provide examples and resources that can be leveraged to build out your own environments on AWS.

With the rapid growth in design complexity and demands of leading process nodes, the compute and infrastructure needs for next-generation designs pose new, daunting challenges. That’s In this presentation, a new layout automation flow dedicated for analog design is introduced. The key technology adopted is the module generator (ModGen), a powerful placement utility in Virtuoso Layout Suite GXL. With this flow, user can generate predefined layout structure which meet foundry DRC without paying a lot customized patch development. This enable more efficiently process porting.

In this presentation, we will talk about a top-down approach to analog mixed-signal system using MATLAB and Simulink, including behavioral modeling, rapid design exploration, predesign analysis, verification and the integration to the Cadence Virtuoso IC implementation system.

This speech will introduce to you the Cadence IP R&D team and Cadence's complete IP solution. At the same time, the video will also share with you the latest industry trends, as well as Cadence's industry-leading technology and product information. In this video, you will also learn about Cadence's localization strategy. Cadence is porting more and more advanced IP technologies and products to domestic advanced processes. Cadence's technical experts will also focus on introducing high-speed DDR IP and SerDes IP solutions based on domestic advanced technology, and conduct live demonstrations in the laboratory to give you an in-depth understanding of Cadence DDR and SerDes products and research and development.

The level of automation of a vehicle is the key driver of the E/E architecture, sensor architecture, automated driving platforms and the electronic content of a car. It’s obvious that future cars will be equipped with more computing power, AI-based systems, car-to-car communication technology, high-bandwidth Ethernet networks, and digital cockpits.
Radar, Lidar and Camera are the key sensors to enable fully autonomous driving. However these sensors still need to be significantly improved in terms of resolution, power consumption, safety, form factor and cost but will also evolve to address new compute architectures.
All these new technologies will dramatically increase the complexity of electronic systems which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. As a result, a new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) is needed to process all sensor data and fuse them together to enable vehicles to become “aware” of their surroundings.
While high-end automotive SoCs have been already designed in 7nm some companies are preparing already their next-generation process technology at 5nm.
Cadence's Automotive solutions can help you to enable such highly integrated systems that can make cars safer and more reliable. This talk provides an overview on automotive trends and the implications for SoC and System enablement for Sensors and Advanced Driver Assist Systems (ADAS).

At advanced process nodes (e.g., 6nm node), circuit design/implementation schedule and timing convergence remain challenging tasks during the physical design phase. Additionally, the placement stage can be one of the most important and most time-consuming steps in the physical design implementation flow, since circuit timing and routing congestion must be considered during this stage. Therefore, in order to consider physical layout effects during the circuit synthesis phase, it is preferred to adopt a full flow, which bridges the quality gap between physical-aware circuit synthesis and physical placement for reducing design iterations. The iSpatial integrates Innovus Implementation System’s GigaPlace placement engine and the GigaOpt Optimizer into Genus. Through the unified core engines inside iSpatial, the circuit design performance can be accurately predicted at the circuit synthesis phase, faster turn-around time for RTL regression can thus be achieved. Moreover, only purely incremental optimization steps after iSpatial need to be applied, that is, the full flow has achieved the overall reduction of total design time. In this presentation, we shall share our iSpatial-based design flow, relevant tool settings, and results of our designs using traditional design flow versus iSpatial-based full flow.

For hierarchical design with low power schemes, each block has its own power state table (PST) and all block’s PST are integrated by EDA tools, that is, to expand all PSTS into a SoC level PST according to IEEE standard definitions. This method induces two problems. First, SoC level PST result goes beyond human’s imagination while integrating a big enough design, e.g., over 10 blocks. Second, there is no clue to tell user why zero, incomplete or 100X size PST happens at SoC level PST. Incomplete PSTs can impact low power implementation and verification quality whereas integration with 100X power states can make CLP (Conformal LowPower) run time become 2X to 10X longer. Based on our experience, manually debugging such issue for a 10+ blocks design with 100+ power states usually cost 2~3 weeks. Hence, we propose a solution including two parts. First, a debugging flow based on CLP to find the root cause of incomplete or oversize PST. Second, MTK PST integration results to let user aware unexpected PST size. By adopting our solutions, integrators can efficiently complete SoC level PST integration instead of try-and-error, and therefore, reduce not only the trail period from 2~3 weeks to 2~3 days but also the size of SoC level PST to user’s expectation.

Over a decade ago, physically-aware synthesis technology was announced and heralded a new era from logical synthesis to physical solution. Before the technology involving, wire R/C (Resistance and Capacitance) is modeled by WLM (Wire Load Model) which is generated by statistic results from foundry. With the technology, wire R/C (Resistance/Capacitance) accuracy can be dramatically improved because it performs real placement and extract wire R/C based on specific physical locations. Therefore, synthesis results can be close to the ones at PD (Physical Design) placement stage, design over-constraint and over-optimization as WLM synthesis are un-necessary. However, at advance process nodes, process design rules become much more complicated than previous. This thing impacts physically-aware synthesis seriously. In real cases, we can see very different results between synthesis and after cell placement. So, we realize that that considering placement and physical location are not enough to advance process nodes. Even using physically-aware synthesis, over-constraint and over-optimization are still necessary like WLM synthesis, advantage of physically-aware synthesis is disappeared. In this work, we discover key items to impact physically-aware synthesis accuracy. Based on the findings, we compare the engine/flow differences between Cadence older synthesis solution and the latest one, Genus iSpatial. Furthermore, we can see that Genus iSpatial has significant improvement in PPA (Performance, Power, Area) correlation from real project cases. With the improvement, we can also see the benefit to timing closure and PPA. Finally, we can give advice about Genus iSpatial for further quality enhancement.

MediaTek is the largest fabless IC design house and have different product lines. As chip becomes larger and complex, power integrity analysis has become dominating stage on time-to-market. To meet the requirement of tape-out schedule, we focus on critical items about capacity, run time and efficient working model. In this session, we show Cadence Volta’s technologies about hierarchical IR-drop analysis with XPGV model and power-DP.
About hierarchical IR-drop analysis, it’s new technology to simplify the Power/Ground mesh saving as XPGV model without accuracy loss. We present XPGV model generation, XPGV model accuracy and runtime reduction. The results show that IR-drop difference is smaller than 1% comparing between fully flatten IR-drop analysis and hierarchical IR-drop analysis which reduces around 50% runtime of rail analysis based on different setup of #XPGV model.
Furthermore, Cadence Voltus provides a distributed platform to do the power calculation called power-DP. It reduces about 50% peak memory and 30~70% run time of power analysis. Thus, we are able to use multiple small machines to handle large designs.
At the end of our session, we propose an efficient working flow and demonstrate how to handle large design to meet the tighten tape-out schedule.

The 112g LR(Long Reach) & XSR (eXtreme Short Reach) SerDes(Serializer/Deserializer) are designed for next generation data center ASICs. Due to the high bandwidth, high speed data transmission behavior, the power consumption of every design part has to be reviewed carefully. In this presentation, we'll show how we implement designs with Innovus pattern-based power optimization to save both switching & internal power of each stage. Moreover, we try to reclaim every possible power with PBA sign-off timing by Tempus total power ECO and finally meet our goal.

Machine Learning is a new skill to improve postRoute timing, SOD is very powerful for AOCV timing closure in Innovus. We apply these 2 skill in our UMC 28nm process and have got good result.

Rigid-Flex PCBs have been used in many modern electronic devices (such as mobile phones, laptops, and wearables, among others), due to their form factor, light weight, and cost-effectiveness. Electromagnetic (EM) analysis of Rigid-Flex PCBs has always been a challenging task for many commercially available 3D numerical solver technologies (FEM and FDTD), due to the complexity in the 3D designs. Much of the complexity comes from bending of the board into small spaces and usage of hatched ground and power planes. In this paper, we first address the key challenges faced by the EM engineers and then propose a novel automated simulation workflow for a fast-to-market product development process. The proposed workflow, utilizing Cadence® Allegro® PCB Editor and Clarity™ 3D Solver, is the first of its kind in the PCB-EM community. Compared to alternative, highly manual processes, this flow is less error prone and very efficient in setting up the design for EM simulation. In addition, it runs faster than the other legacy 3DEM tools in the industry.

As the semiconductor manufacturing technology keeps scaling down, the power density of modern microprocessors is increased because of more transistors available within the same die area. The hotspots can be induced by the high power density in a smaller die area and be considered the primary causes of extremely high junction temperature. Modeling the package only thermal model may lead to inaccurate temperature estimation because the TIM, heat spreader and heat sink can significantly affect the die temperature and temperature distribution. This study established thermal model by Cadence Celsius Thermal Solver, which includes the printed wire board, package, TIM, heat spreader and heat sink for more accurate die temperature evaluation

TSMC plays the leading role of providing advanced packaging and chip staking solutions benefiting customer to unleash their design innovation with smaller form factor. The TSMC-Cadence collaborated flow and methodology to boost the design productivity on 3DIC will be mentioned.

5G, IoT, automotive and datacenter is rapidly expanding need for simulation. The form factor is shrunk, and design complexity is increased while the signal transmission speed is increased continuously. To meet time to market with good accurate sign-off flow, more and more design requires true 3D electromagnetic modeling. Cadence Clarity 3D is an innovative full wave solver providing accurate and fast modeling for chip, package, connector and system board. A massive parallel computation technology can leverage existing machine resource and less memory to complete a complicated model extraction. Allegro and Clarity integration provides a very efficient and accurate model for rigid-flex board designs.

Growing demand of low cost and high performance 2-layer board design can be found on current HPC and high-definition TV applications. To achieve successful 2-layer board design, it is strongly relied on 3D electromagnetic simulator with gold-standard accuracy to estimate all non-ideal effects completely. In this talk, a 2-layer PCB design for high speed DDR4 system is demonstrated with highly accurate S-parameter model extracted by Clarity 3D Solver.

In the IoT ecosystem, the wireless sensing network plays an important role in data acquisition and data transmission to communication cloud computing networks, of which RF technology is the key to affect the effectiveness of wireless sensing networks, from radar sensors, antenna design, wireless channel link budget and interference analysis, wireless transceiver design (filters, power, low noise amplifiers), modulation technology, power integrity and even electrothermal analysis. All will affect IoT coverage, signal quality, battery and construction costs. This presentation will show how Cadence's range of system analysis EDA tools can help designers overcome these challenges.

Accompany with 5G development, RF module design will meet more challenge in linearity, power and heat necessary to be successfully in the handset market. How to get efficient and accurate EM model will help designer to shorten the design cycle and bring to market better products with less risk. This presentation will introduce a new RF solution -EMX Planar 3D Solver to overcome the upcoming 5G’s difficulty.

Conformal antennas used in modern mobile platforms require in-situ tuning and optimization. The antenna performance and frequency response are significantly impacted by the various elements of the platform including the case, display, and other metallic structure to the antenna. Since the versatile of modern mobile devices, the components and structures are ultimately close to the antenna. The full-wave 3D solvers must be utilized to accurately model in-situ antenna response prior to design signoff. Beyond the requirement for in-situ antenna analysis, density of modern mobile designs force engineers to also simulate antenna de-sense response. RF and high-speed digital signals radiating off boards, packages, cables, and connecters inside the mobile device couple to the antenna and can significantly degrade the performance of radio receivers. In this talk, the illustration for Clarity 3D field solver can be utilized to perform efficient and accurate analysis of mobile antennas in-situ, and incorporate radiating boards, package, and connectors to model complex de-sense analysis.

5G comes to reality, change the whole industry, including the RFIC & RF component design. In this new era, PA, filter, antenna designers need to face the challenge of beamforming, phase array, OTA measurement and ensure time-to-market schedule. In this presentation, we will introduce key measurement challenge in 5G & mmWave design; including beamforming method, multi-path component measurement and OTA test. Next, we talk about how to leverage R&S instruments & Cadence EDA tool to accelerate the design and overcome the measurement challenge.

This portion of the talk will take a closer look at the EM analysis of an 8-element phased array design intended for use in a 28 GHz handset reference design imported from Allegro PCB Designer into AWR Design Environment. PCB import editing capabilities are used to prepare the structure and define excitation ports for accurate simulation and generation of far field plots. Considerations such as proper port and ground definitions and passivity checking will be discussed. An alternative design based on a 4x1 dual polarized design targeting antenna in package (AiP) will also be presented.

Mr. Philip(Ming-Fu) Tsai joined Global Unichip Corporation since Sep. 2017 and currently serves as the DV Director. He is responsible to lead Design Verification team to incorporate the state-of-the-art verification methodology to verify SOCs for the application of AI & High-Performance Computing. His team defines and develops DV methodology and flow for GUC’s SoC project which incorporates the up-to-date DV techniques such as UVM, Formal Verification, X-Verification, Assertion Synthesis, and Emulation. He has more than 16 years Design Verification experience on verification methodology/solution for delivering product with highest quality. He served as Senior DV Manager of Switching Products Division at Broadcom Taiwan Design Center, responsible for project DV of every Ethernet Switch, Network Processor, and IPs developed by ING/CSG in Taiwan. He formed up and managed Design Verification team at Broadcom Taiwan Design Center since April 2008. In 2001, Mr. Philip(Ming-Fu) Tsai graduated from National Tsing Hua University with a M.S. degree in Electrical Engineering.

Customers frequently change and add design specification, which is common for on-going projects. To catch up with the same taped-out schedule, it is really a tough challenge for traditional RTL design flow and engineers usually work overtime under a lot of pressure for modifying RTL for new specifications and considering better architectures for ultra-low power requirements. In this presentation, we would like to share how do we overcome such challenge from the customers to meet the same taped-out schedule with efficiency and low risk by a high-level synthesis (HLS) based design flow. Configurable SystemC design can easily be switched to various specification under the same codebase. In addition to optimizing pipelined designs for various design specification, Stratus-Joules flow also facilitates to explore better low-power architectures to meet the customers’ specifications.

Prototyping platform is essential for early FW & SW development. However, traditional prototyping solution requires long bring-up time especially for large SoC design due to design re-modification, PnR timing closure & limited debug capability. Protium’s unique automatic compile flow accelerated HW/SW integration process and enabled the software development of SoC designs earlier than before. The platform also allowed user to boot Linux and Android faster and run AnTuTu benchmark scoring in half a day. In addition, the platform shares a common compile flow with the Cadence Palladium Emulation Platform, which allows us to re-use our existing Cadence verification environment and achieve functional congruency between the two platforms.

USB3 VIP Adoption speech provides VIA Labs, Inc. experience at Cadence USB3 VIP. The first is USB3 specification brief introduction. This provide simple introduction from USB 2.0 to USB 3.2. Next section explains why verification methodologies like SystemVerilog, UVM, and Cadence VIP are chosen. Some verification experiences are shared. Final is conclusion about why VIA Labs, Inc. recommend Cadence VIP solution.