CadenceLIVE India – OnDemand
Keynote
Fueling the Data-Centric Revolution
CadenceLIVE: India-Keynote
Lip-Bu Tan, CEO, Cadence
1
Keynote: Computational Software for Intelligent System Design
CadenceLIVE: India-Keynote
Dr. Anirudh Devgan, President, Cadence
2
Guest Keynote: Cadence and Academia: From Transistors to Systems with Computational Software
CadenceLIVE: India-Keynote
3
Custom and Analog Design: Implementation
A Common Platform for Generalizing, Capturing, Analyzing, and Exporting Custom Structures Across PDK and Designs Using Circuit Prospector
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI01
An Automated and Reliable Methodology to Check Shielding of Sensitive Signals in Analog Layouts
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI02
CLE (Concurrent Layout Editing, a New Advanced Methodology for the Next Generation of MSot Smart Power (BCD) Design
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI03
Design-Driven Analog Layout Methodologies Using Virtuoso XL 18
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI04
Developing Correct-by-Construction Standard Cells Using Virtuoso Pin Accessibility Checker
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI05
7_Intel_Improving Design TAT and Reliability by Adding Electrical Awareness Early in Design Cycle
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI06
Technology Update - Thinking Beyond The Chip
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI07
Virtuoso Environment-Based P&R for Standard Cell - Based Layouts
CadenceLIVE: India - Custom and Analog Design: Implementation
CADI08
Custom and Analog Design: Verification
Advanced Methodology for Accurate EM-IR Analysis in Voltus-Fi XL
CadenceLIVE: India - Custom and Analog Design: Verification
CADV01
Functional Verification of a PMU
CadenceLIVE: India - Custom and Analog Design: Verification
CADV02
Mismatch Analysis and Tuning for Analog IP with Virtuoso Variation Option
CadenceLIVE: India - Custom and Analog Design: Verification
CADV03
Methodology for Accurate Design and Verification of High-Speed Delta Sigma ADC's with Virtuoso ADE Assembler, Spectre X, and Voltus-Fi Technology
CadenceLIVE: India - Custom and Analog Design: Verification
CADV04
Multi-User Flow in Analog DV Using Setup Library Assistant and Virtuoso ADE Verifier
CadenceLIVE: India - Custom and Analog Design: Verification
CADV05
Streamlined Flow for Enabling Instance-Based Multi-Technology for Mixed Simulation Designs
CadenceLIVE: India - Custom and Analog Design: Verification
CADV06
Taking the Analog Simulation Performance to the Next Level Using Spectre X Simulator
CadenceLIVE: India - Custom and Analog Design: Verification
CADV07
Technology Update - Spectre Simulation Platform
CadenceLIVE: India - Custom and Analog Design: Verification
CADV08
Digital Front-End Design
Advanced Static Low-Power Verification Topics and Methodology
CadenceLIVE: India- Digital Front-End Design
DFD01
Better Predictability and PPA with Genus iSpatial Technology
CadenceLIVE: India- Digital Front-End Design
DFD02
Efficient Handling of Super Under Drive Corner with Genus iSpatial at Lower Tech Nodes
DFD03
Embracing Conformal ECO Designer Over Indigenous Manual ECO
CadenceLIVE: India- Digital Front-End Design
DFD04
Extending Innovation with Joules RTL Power Solution and Conformal Formal Verification Solution
CadenceLIVE: India- Digital Front-End Design
DFD05
Improved TOPS per Watt in Computer Vision Products Through PD Power Optimizations
CadenceLIVE: India- Digital Front-End Design
DFD06
Modus DFT – Solving the Physical Problems of Test
CadenceLIVE: India- Digital Front-End Design
DFD07
Novel Methods for Achieving High Coverage with Low Test Time Using LBIST at SoC Level
CadenceLIVE: India- Digital Front-End Design
DFD08
Power-Aware Scan Architecture Using Low-Power Gating Compressor
CadenceLIVE: India- Digital Front-End Design
DFD09
Synthesis Methodology to Achieve Best-in-Class Performance and Power on Complex Low-Power Designs
CadenceLIVE: India- Digital Front-End Design
DFD10
Digital Implementation and Signoff
Accelerating the Power Signoff Challenges in 7nm Complex Multi-Million SoC Designs in Voltus IC Power Integrity Solutions
CadenceLIVE: India- Digital Implementation and Signoff
DIS01
A Cookbook for Aggressive Area Reduction Strategy on Arm Cortex-A55 CPU Core Using Cadence Implementation, Power, and Signoff Solutions
CadenceLIVE: India- Digital Implementation and Signoff
DIS02
Chip Reset Methodology for Optimal Digital Design Implementation and Signoff
CadenceLIVE: India- Digital Implementation and Signoff
DIS03
Clock Tree Synthesis Using Flexible Structured CTS for Complex Clocking, High Divergence, and Highly Rectilinear Floorplan
CadenceLIVE: India- Digital Implementation and Signoff
DIS04
Custom Clock for Network on Chip Architecture
CadenceLIVE: India- Digital Implementation and Signoff
DIS05
Extending Power, Performance, and Area (PPA) Leadership using Machine Learning
CadenceLIVE: India- Digital Implementation and Signoff
DIS06
Leakage Power Recovery of a High-Frequency MIM-Based Processor Design Using Tempus TSO-ECO Signoff Solution
CadenceLIVE: India- Digital Implementation and Signoff
DIS07
Technology Update - Digital Full Flow Innovation Delivering Design Excellence
CadenceLIVE: India- Digital Implementation and Signoff
DIS08
Tempus Power Integrity: A True Signoff Solution for Concurrent IR Drop and Timing at Lower Nodes
CadenceLIVE: India- Digital Implementation and Signoff
DIS09
Tempus SmartScope-Based Hierarchical Analysis and Closure
CadenceLIVE: India- Digital Implementation and Signoff
DIS10
IP/Subsystem Verification: Performance and Smart Bug Hunting
Accelerating SoC Verification Signoff Using SNR/DTR Enhanced Regression Flow
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
ISVP1
Accelerating Verification Productivity by Harnessing Latest Xcelium Simulator Performance Improvement Methodologies
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
ISVP2
Code Coverage Metric Signoff and Integrating JasperGold Coverage Unreachability (UNR)App Flow in vManager Simulation Regression Environment
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
ISVP3
Experience of Using Formal Verification for a Complex Memory Subsystem Design
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
ISVP4
New Paradigm for Improving Verification Productivity, Emerging as an Aided Workforce, Using Xcelium Save and Restart Feature
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
ISVP5
Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
ISVP6
Verification of LPDDR5 High-Speed Memory Controller and PHY Using Cadence Denali VIP
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
ISVP7
PCB Design and System Analysis
Accurate S-Parameter Extraction and Analysis for Rigid-Flex Board with Wirebonded CoBs
CadenceLIVE: India- PCB Design and System Analysis
PCB01
Achieving High Throughput and Design Efficiency with Allegro Productivity Toolbox Solution
CadenceLIVE: India- PCB Design and System Analysis
PCB02
Cadence AWR Design Environment: A Simulation Platform for RF and Microwave Designers
CadenceLIVE: India- PCB Design and System Analysis
PCB03
Modeling and Simulation Challenges of DDR5/LPDDR5 Interfaces and Enabling DFE Techniques Using Sigrity Technology
CadenceLIVE: India- PCB Design and System Analysis
PCB04
Optimizing Gate Drive Circuits for Automotive Applications Using PSpice A/D
CadenceLIVE: India- PCB Design and System Analysis
PCB05
Signal Integrity Analysis of HBM2E-Based Silicon Interposer Using SystemSI
CadenceLIVE: India- PCB Design and System Analysis
PCB06
Technology Update - Data-Driven System Design and Analysis
CadenceLIVE: India- PCB Design and System Analysis
PCB07
USB 3.0 Electrical Compliance
CadenceLIVE: India- PCB Design and System Analysis
PCB08
Zig-Zag Routing for High-Speed Signals 20GBPS
CadenceLIVE: India- PCB Design and System Analysis
PCB09
SoC Verification: Advanced Verification Methodology
Accelerating ATPG Simulations Using Xcelium Multi-Core Simulator
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
SoC01
Enhanced Test Bench Architecture for Robust PHY Verification Using PHY Monitor
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
SoC02
Invited Paper Faster Regressions Using Xcelium with Machine Learning
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
SoC03
New Parallel/Incremental-Build Paradigm Leading to More than 11X Gain with Parallel Compile and 7X with Parallel Elaboration Using Xcelium Features
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
SoC04
Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
SoC05
System Design and Verification: Emulation and Prototyping
GSP Emulation with Palladium Platform and Prototyping with Protium Platform
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
SDVE01
Improving Firmware Validation Productivity and Debug Efficiency Using Palladium Z1 Platform and Indago Debug Analyzer
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
SDVE02
SoC Firmware Debugging Tracer in Emulation Platform
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
SDVE03
Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
SDVE04
System Design and Verification: Flows
Acceleration of Coreless SoC DV Using PSS with Superior Coverage on Multi-Link PCIe Subsystems
CadenceLIVE: India- System Design and Verification: Flows
SDVF01
Advanced Mixed-Signal Modelling Methods Using System Verilog for Efficient System-Level Verification: Challenges, Opportunities, and Enablers
CadenceLIVE: India- System Design and Verification: Flows
SDVF02
Quicker Verification Signoff for Nested Networks-on-Chip (NOCs) in Complex SoC
CadenceLIVE: India- System Design and Verification: Flows
SDVF04
Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- System Design and Verification: Flows
SDVF05