This study introduces a lock-in integrated controller for resonant SCC. The controller identifies the resonant period of each sub-circuit on-the-fly and locks-in to the correct switching time to fully utilize the charge transfer rate for each flying capacitor. The various modules of the controller are detailed, including the auto-tuner and sequencer which accommodate any mismatch, variations or drifts of component values or circuit configuration. The IC has been designed and fabricated on a 0.18µm 5V process resulting in effective silicon area of 0.64mm2. Experimental results of the controller IC operating in closed-loop are provided, demonstrating accurate lock-in for two resonators with individual independent resonant characteristics.  A full-scale hardware prototype of 650W 4:1 switched-tank converter is used to validate the controller’s operation, demonstrating excellent lock-in capabilities resulting in high efficiency of up to 98.6%.

As a building block of an E-band receiver, a quadrature voltage-controlled oscillator (QVCO) in Colpitts topology is presented, promising low phase noise due to an innovative coupling mechanism between two differential cores. The passive, capacitive coupling avoids the introduction of additional active devices and operates in-phase, using injection locking. A prototype with heterojunction bipolar transistors (HBT) in 0.13µm SiGe BiCMOS technology obtains an output power of 2 x 0dBm differential and a phase noise of -104dBc per Hz at 1MHz offset, with 39.5GHz mean frequency of oscillation. The frequency tuning range is 6.4% and power efficiency 1.25%. The robustness of the quadrature coupling, and oscillator performance is proofed by simulations and verified by frequency and time domain measurements of the prototype.

Nowadays, due to the emergence of Internet of Things, the number of sensor nodes employed in wireless sensor networks, increases exponentially. The energy harvesting concept provides a viable solution regarding the power supply and energy autonomy of such networks. In this work, a reconfigurable supercapacitor storage scheme, suitable for energy harvesting applications is presented. The structure is comprised of two supercapacitors, a small and a larger one, four switches and the control unit, responsible for the reconfiguration of the scheme. The critical parameters for the system’s reconfiguration are the small supercapacitor’s voltage level and the ability of the overall system to sufficiently supply the load. The system’s design was carried out in 0.35um CMOS technology. This highly efficient architecture provides a fast supply of the load and output voltage pre-regulation.

Modern, digital hearing aids contain a large number of adjustable parameters. For example, currently it is possible for the hearing aids to process parts of the incoming sounds in order to improve the sound quality for the hearing impaired by e.g. amplifying or reducing specific parts of the incoming sound. There is a trend to perform automatic speech recognition in hearing aids for e.g. device control or algorithmic parameters optimization. Moreover, automatic speech recognition is often encountered in daily life. For example, users can control their smartphones or their smart home containing lights, heaters or vacuum cleaners by voice commands.

The state of the art is the use of neural networks for automatic speech recognition. A widely used architecture is the fully connected neural network . This work proposes a configurable and scalable hardware coprocessor for phoneme classification in the low-power embedded domain of the hearing aid. This hardware coprocessor accelerates a sparse fully connected neural network and uses the sparseness to optimize memory storage requirements and performance. The proposed hardware coprocessor is evaluated regarding performance and area.

We present a 2 x 100 W GaN FET full-bridge Class-D stereo audio amplifier designed by a team of six Power Electronics and Microelectronics Master students at Reutlingen University within a one-year laboratory project. The circuit comprises EPC2103 GaN half-bridge devices switched at about 750 kHz by a CMOS modulator ASIC and Silicon Labs gate drivers. The modulator ASIC was designed by the students in X-FAB's 0.35-µm mixed-signal CMOS process XH035 using Cadence Virtuoso and ADE/Spectre for schematic entry, simulation, and layout. We show how a student project team that starts from almost zero knowledge of IC design and Cadence EDA software can successfully produce a tape-out-ready analog IC design within just four months and integrate their own chip in a complex board design within one year. Key success factors include a consistently preconfigured, ready-to-use Cadence IC design environment for the student project team, an experienced team of scientific and technical advisors as well as X-FAB's silicon-proven analog IP libraries and reliable MPW schedules.

Power consumption is a major concern in todays System-on-Chip (SoC) design and verification. While functional verification on system-level has recently be pushed to higher levels of abstraction using behavioral models, verifying power consumption still relies on time-consuming low-level simulations. This contribution presents a novel methodology for augmenting purely functional models of AMS blocks with information about their transient power consumption without manual interaction. This is realized through machine learning from simulations of the corresponding transistor-level representation. A neural network regressor is trained and afterwards automatically translated into a behavioral modeling language that is compatible to industrial circuit simulators. The applicability of our approach is presented in a case study.

Traditionally, digital circuits are designed for a worst operating condition case, which limits the performance when working under relaxed conditions. In this work, timing speculation is used to improve the performance of a high-temperature DSP in better-than-worst-case environments. Correct circuit operation is ensured by a timing error detection and correction mechanism at circuit-level, which is integrated into an ASIC implementation flow. The presented case study for a 1µm high-temperature SOI CMOS technology shows DSP processing performance improvements of up to 14.25% under non-worst-case conditions while executing an OFDM encoding algorithm.

Many view location tracking to be one of the killer apps for IoT.  But advanced logistics, transportation, smart city and smart factory applications strain the current class of solutions, often designed with smartphone or vehicle navigation in mind.  These solutions fall short in terms of power consumption, cost and coverage indoors.  Based on advanced signal processing algorithms and a hybrid device/cloud architecture, Nestwave has developed a low-power geolocation solution that eliminates the need for a dedicated positioning chipset.  When combined with the efficiency of the Cadence Fusions DSP , geolocation performance is improved with substantially reduced power consumption.Power to cost

In this case-study, fault simulation is performed on an analog buffer by injecting random faults on device level. These randomly generated faults are grouped into different categories, while the simulation results can be splitted for different failure groups that gives an insight of the circuit behavior. As an end result, the outcome of the simulation gives the safety performance of the buffer for the considered fault groups which is defined by automotive standards. This results can be used to rate the functional coverage and safety performance of this particular analog block.  Legato reliability solution is used with its Rapid Adaption Kit (RAK) as a guideline for fault simulation in this case-study. The design example for analog buffer is designed on TSMC 180 nm BCD technology.

Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data center and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our high speed portfolio to include PPA-optimized 56G-LR in TSMC N7/N6 processes to address the connectivity needs of the 5G infrastructure and AI/ML market and have all the building blocks to accelerate the adoption and deployment of cost-effective 100G and 400G networks as well as a trajectory to a 25.6T switches. However, not all PAM4 high speed SerDes are born equal. In this presentation, we will share with you the various flavors of LR, MR/VSR and XSR high speed SerDes and where they fit best in the end application space. You will also learn the tradeoffs between data rate, power, performance, area, insertion loss, and flexibility of use to help you decide the right PAM4 SerDes for your next design.

The bulk of this presentation will focus on physical implementation of the Cortex-A76AE processor core using advanced features of Cadence RTL to GDS2 digital implementation tool chain in 7nm.

This presentation examines several case studies in which RF/microwave engineers have used design software to address a range of challenges in developing high-frequency components and systems for various automotive applications and supporting antenna systems. These case studies include the use of 3D finite element EM analysis to accurately model a wireless tire pressure sensor, matching impedance network development for a low-noise amplifier (LNA) design for an SDARS receiver, and the use of EM analysis to perform an electromagnetic compatibility (EMC) simulation of an automotive navigation/audio system.

The presentation details how a Tensilica, i.e., Fusion F1, based system is realized in 22 FDX from GlobalFoundries. The SoC operates at an aggressively scaled single supply voltage of 600 mV, which powers both the logic and the memories. It is demonstrated how Xenergic’s SRAM offers best-in class power efficiency, by offering a leakage and access power optimized memory with foundry bitcells. Xenergic’s low-power SRAM enables aggressive voltage scaling of the entire SoC, and the single-rail implementation strategy reduces engineering, integration and area cost. Static power consumption of the entire SoC (processing logic and SRAM) is significantly reduced. The square dependency of the dynamic power on the supply voltage will result in dramatic dynamic power savings. The study shows that Xenergic’s industry leading SRAM technology is a key enabler for highly optimized Tensilica-based systems.

By implementing radar technology over the 76-81GHz spectrum, advanced driver assist systems (ADAS) enable smart vehicles to alert and assist drivers in a variety of functions, from smart cruise control and collision avoidance to self-parking. These automotive radar applications use the millimeter-wave (mmWave) spectrum to exploit more bandwidth for greater resolution and object detection. However, higher frequency propagation comes with greater path loss, as isotropic free-space attenuation is inversely proportional to wavelength. In addition, along with this additional path loss, as wavelengths get smaller, physical processes such as diffraction, scattering and material penetration loss make the channel properties of mmWave bands significantly more challenging. This presentation examines the radar technology commonly found in ADAS systems and highlights a design example that illustrates how a basic frequency-modulated continuous wave (FMCW) radar system operates. The combined use of system, circuit, and EM tools to overcome the challenges in mmWave (77 GHz) automotive radar design and phased array antenna development is discussed.

The level of automation of a vehicle is the key driver of the E/E architecture and the electronic content of a car. It’s obvious that future cars will be equipped with more computing power, AI-based systems, car-to-car communication technology, high-bandwidth Ethernet networks, and digital cockpits. Radar, Lidar and Camera are the key sensors to enable fully autonomous driving. However these sensors still need to be significantly improved in terms of resolution, power consumption, safety, form factor and cost but will also evolve to address new compute architectures. All these new technologies will dramatically increase the complexity of electronic systems which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. As a result, a new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) is needed to process all sensor data and fuse them together to enable vehicles to become “aware” of their surroundings. While some high-end automotive SoCs have been already designed in 7nm some companies are preparing already their next-generation process technology at 5nm. Foundries claim that 5nm provides about 20 percent faster speed or about 40 percent power reduction and is perfectly suited for the next generation of automotive processors. Cadence's Automotive solutions can help you to enable such highly integrated systems that can make cars safer and more reliable. This talk provides an overview on automotive trends and the implications for SoC and System enablement for Sensors and Advanced Driver Assist Systems (ADAS).

With the rapid growth in design complexity and demands of leading process nodes, the compute and infrastructure needs for next-generation designs pose new, daunting challenges. That’s why every high-performance team is looking at Cloud with great interest. The scalability and agility offered by cloud addresses many of the gaps in design infrastructure. However, transitioning to cloud requires thoughtful decisions about cloud architecture, data management, infrastructure setup, security, to name a few.

In this session, we will discuss the pros and cons of various cloud architectures, their suitability for design flows and IT needs for successful cloud transition. We will also describe the Cadence Cloud solutions used by over 100 customers to successfully embrace cloud for their production designs.

This talk will address TSMC’s brand new Cloud strategy of Scale-Out and Scale-In for timing sign-off, helping customers to speed up run-time in a big way while achieving cost saving at the same time. By injecting in-depth Cloud and IT knowledge into OIP EDA enablement, TSMC & its Cloud Alliance members Cadence and Microsoft jointly created Cloud-optimized design solutions in Tempus and Quantus with concrete benefits validated using Microsoft’s latest VM(virtual machines) newly announced mid-year 2020 targeting EDA runs. TSMC Cloud Alliance white paper on the subject is of immediate availability for customer download from the portal of TSMC-Online (online.tsmc.com).

Memories are used in a wide range of applications from wireless networking and consumer entertainment solutions to automotive. High performance is required for some, while low power consumption is the main objective for others. To accommodate this wide range of constraints,  the memory should be very flexible in terms of size and aspect ratio and very dense to minimize the area. The target process varies from mature node to advanced node using planar or FinFET transistors.

For more than 15 years and thanks to the expertise of its layout designers, Arm Physical Design Group has been a leading library provider, delivering high density complex memory compilers, meeting a wide range of applications constraints. Arm layout teams have an extensive experience of using Virtuoso starting with its early versions (like 5.1). Due to the tight development schedule constraints and advanced design rules complexities, designers must venture outside of the basic and be more efficient.

After collecting the log files of a pilot project’s virtuoso sessions, it became clear that more productivity could be achieved through the introduction of new functionalities in latest version of Virtuoso (18.1), especially the ones focusing on advanced node layout methodologies. Cadence R&D/PE and Arm Physical Design Group Layout teams partnered to identify and prioritize the features that would benefit the layout designer productivity the most.

For advanced node usage, we converged to a connectivity driven assisted routing and automation of via placement and coloring. We put in place short training sessions, monitored the usage of these recommended features and their impact on productivity. After six months of collaboration, layout productivity has been improved up to 40% on advanced node with very restrictive rules using width spacing pattern (WSP) and row-based methodology. This collaboration has been extended world-wide to the broader Cadence and Arm teams.

The complexity of the SoC increases with the new demands of performance and safety from the market. Although with System Verilog User-Defined Nettype, such as Cadence’s EEnet, it’s possible to develop real-number models (RNM) which represents load effects and execute exhaustive Digital-Mixed-Signal (DMS) simulations to improve system functional checks. The leakage path and capacitive loading from top-level connection, non-linear behavior and process/temperature dependence of analog circuit are usually not covered by RNM. These figures are intrinsic of analog simulation. With an advanced analog simulator and well-considered partitioning of signals into discrete and continuous domain, it’s possible to simulate the Power Management Unit (PMU) blocks in spice netlist at chip level within 1 hour, which makes AMS be an executable complementary verification method on top of DMS with RNM.

Unlike digital verification with matured methodology such as UVM, analog verification mainly relies on manual inspection, usually comparing waveforms against requirements. Although there is a self-checking method developed in Verilog-A for analog signals with assertions; the language itself, Verilog-A, does not compete with dedicated assertion languages e.g. Property Specification Language (PSL) and System-Verilog Assertion (SVA). The self-checking method presented in this presentation is implemented with SVA modules which are tuned for analog behaviors. On one hand, the mature assertion development from digital verification is reused for inspecting the analog signal; on the other hand, the data processing and assertions are no longer executed by the slow analog simulator, so the overall simulation time of AMS is reduced.

In the traditional analog testbench setup, the stimulus and loads are implemented with discrete components such as voltage sources, current sources, resistors and capacitors, etc. This type of setup has the following disadvantages: hard to synchronize different sources and loads; stimulus does not self-adapt to process/temperature variations; dard to create complicated test patterns with DUT inside a closed loop; one testbench can only serve limited number of test scenarios, in other words, multiple testbenches are required to cover the verification plan. To overcome these weaknesses, a single code-driven stimulus module implemented by Verilog-AMS is proposed in this presentation to drive and load the DUT. Inside the stimulus module, there are probes to covert the analog signals to discrete domain to feed the SVA checkers; and a built-in asynchronous finite-state-machine (A-FSM) to control stimulus based on the read-out from the DUT, thus a closed-loop is formed which enables complicated test patterns and self-adaptation. Within Verilog-AMS stimulus code, the testbench configuration can be altered by compiler directives; and the selection of test patterns can be done via if- or case-statement against stimulus module’s parameter. Thus, with proposed testbench built-up, it’s possible to use a single test to cover all the test scenarios, which significantly reduces the developing and maintenance effort.

This presentation demonstrates an analog verification regression at chip level for a Dialog Semiconductor’s product; the regression is implemented via Cadence Maestro Suite (Assembler + Verifier) with Analog-Mixed-Signal (AMS) simulations. A single Cadence Assembler Test is used to synchronize the Verilog-AMS stimulus, checkers and snapshot configuration to cover 30+ test scenarios through the test design variables. The regression summary and results filtering are done via Cadence Verifier by linking the verification requirement and the regression results. The total run-time of regression is less than 10 hours, which enables regular and sign-off check on daily basis. In the end, the silicon has positive measurement results.

Reliability analysis, including EM, IR-drop, and SHE, has become a critical part of the SoC flow, especially at 5nm node.  Cadence Voltus-FI within the ICADVM18.1 Virtuoso design environment provides much needed improvement in the tools and flows for reliability analysis.   The presentation will highlight the design and process files required to complete the flow and the steps to validate the results. We also highlight improvements in ease-of-use.

Modgens have been available in Virtuoso (R) for quite a long time, and have contributed to enhance layout productivity, mainly thanks to their interactive placement interface. For what concerns routing of analog structures (such as current mirrors, cascoded current mirror, differential pairs...) a great deal of effort has been spent by many companies to automate this step, resulting generally in high-quality routing, but dedicated to a very narrow class of problems, using dedicated SKILL/SKILL++ algorithms which development and maintenance requires highly Skilled software engineers (pun intended). This presentation introduces Modgen Algorithmic Abstraction Layer, which comprises of a high-level algorithmic language, associated to graphical representation of routing algorithms, as well as an abstracted API to low-level modgen and routing elements. This technology-independant abstraction eases algorithm design, debug and maintenance, facilitates knowledge capture as well as algorithms sharing and derivation, with little to no knowledge required in the underlying SKILL++ generated code. This presentation details the architecture of solution, including intermediate Design-Specific-Language (DSL) designed to represent algorithms, as well as so-called SKILL++ "bricks" interfacing Modgen Sandbox and routing elements. It also describes the GUI developed to interact with algorithms, enabling "bricks" parameterization,  algorithm capture and execution. This technology has proved to greatly improved analog productivity for Place and Route of elementary analog structure. For example,  a 40nm cascoded current-mirror comprising more than 400 devices can be placed-and-routed, LVS clean, DRC clean while capturing all layout best-in-class practices for this kind of structures in less than 5 minutes, compared to a (measured) 4 hours when done manually by an expert layout engineer. However, more than the productivity gain (which can also be obtained by dedicated SKILL++ algorithm), this method additional interests rely on the focus put on usability (for analog layouters), parameterization (for both advanced layouters and CAD engineers), new algorithms derivations (advanced layout and CAD engineer), and finally ease of algorithm porting to different technologies. This framework represents a breakthrough in analog layout productivity and is under deployment in several ST Microelectronics divisions.

Handing off RTL IP demands a high bar to know what the final physical realization will look like from a power, performance, and area (PPA) perspective. Total confidence in silicon performance prior to customer engagement is critical. For these reasons, we’ve engaged with the new Genus iSpatial flow – improved predictability of physical results, and superior PPA. We’ll discuss the switch from our legacy synthesis flow to Genus iSpatial – including Common UI and Early Clock Flow, and how it’s improved our designers efficiency and end quality of RTL that we deliver to customers, with examples from our latest N7 designs.

The race to compute performance at minimum power is for decades one of the major challenges for electronic design. It now reaches even higher level of priority when considering the increasing need for high performance CPU used in most of the market segments such as HPC, Server, client and Automotive.

Latest technology nodes and advanced Arm cores allows us to reach aggressive PPA targets. Nevertheless, challenges to break 4.0Ghz barrier are numerous and inter-related which translate into complex physical implementation development. To address competitive high-performance CPU market, cores are getting larger in physical size, design complexity and must be implemented with latest technology node.

To push the core to the maximum achievable frequency, we had to optimize and fine-tune physical implementation technics to design, EDA tool and technology node specifics.

As an example, local logic dominated paths benefit from the technology node performance up-lift  but as the opposite, critical paths on latest large cores are extremely difficult to close at high frequency due to their heterogenous nature which combines highly multiplexed logic with large fanin/fanout, and critical memory/transport.
 
As part of a cross-functional initiative with Cadence and Arm CE-CPU group, Arm PDG Advanced Product Development group in Sophia was given the critical task to investigate and find a path to break the 4.0GHz limit.

Through this presentation, after an overview of the context and challenges that were ahead of us when we started this performance push exercise, we will describe how we managed to reach our ultimate PPA target, thanks to a tight collaboration with Cadence and thanks to a thorough investigation on how to best combine the use of very advanced Physical IP, Technology, EDA tools and flow.

CDC checks are an important step in the design flow. Incorrect synchronization can lead to unexpected behavior and broken chips that might require a total respin. Tackling the CDC challenge early in the flow can save several weeks during the design cycle and lots of money in case of bugs in the final chip.

With the advent of Edge AI applications which often embed multiple cores and accelerators, it is now mandatory to have an advanced management of the power optimization during PnR flow.

Dolphin Design has a long mastery in power management and in edge processing IPs. This paper will illustrate how such IPs can be efficiently integrated through advanced  PnR flow. Such know-how enables to achieve breaking energy efficiency levels.

Today design complexity and PPA requirements of modern networking ASICs are constantly growing and IRDrop aspects are becoming more crucial and difficult to fix. This is why it’s fundamental to deal with them as early as possible during physical implementation. Cadence IR Aware Full Flow is the best solution to manage these issues through several Voltus Power Integrity features in Innovus. In this presentation we’ll show STMicroelectronics design experience with two Cadence IRdrop methodologies: IR drop aware placement, to spread local high-power density hot-spots and reinforce PG, to add automatically local PG stripe/via patterns.

GLOBALFOUNDRIES 22FDX fully depleted silicon-on-insulator (FD-SOI) technology offers an optimal combination of performance, low power and cost for mid and high performance CPU based designs powering differentiating solutions in the mobile and pervasive computing space. GLOBALFOUNDRIES has executed several design optimization studies to demonstrate the benefits of GLOBALFOUNDRIES 22FDX technology exploiting the additional optimization space provided by body biasing techniques.

GLOBALFOUNDRIES has developed a family of 22FDX test chips which provides the infrastructure for implementing various SoC CPU cores. The presentation discusses a SoC test chip implementation comprising an Arm Cortex-A53 quad-core CPU and Cadence Tensilica HiFi5 and Fusion F1 cores, which constitute several voltage and body bias domains. The test chip architecture will be introduced including the Adaptive Body Bias sub-systems. Based on the Cadence digital implementation flow, specific decisions are discussed in the areas of DfT, power intent and timing sign-off.

There is no dedicated plan based verification methodology for analog and mixed signal verification.  vManager and vPlanner have been used by digital design engineers to perform digital verification. There is a trend to run top level mixed signal verification using vManager. However, vManager requires regression setup time and scripting skills. Cadence Verifier closes the gap with spec-driven verification for analog circuits.

Verifier is a mixed-signal design verification cockpit. The full design verification cycle can be implemented within Verifier. A verification plan can easily be built up by either importing from design specification or interactively as you go. Plan partitioning allows easy work split tasks and simplifies the simulation regression size. The flow presented applies to a UVM based verification flow. Parametric based specifications are calculated automatically by the scoreboard. The results are ported to expressions though log parsing. Functional checks are performed through event driven simulations and test outcomes are computed by log file parsing. Modifications to the setup are flexible and easily done on the fly. Coverage data is collected during AMSD simulations to ensure the quality of the analog/digital interface. With the new SPACE feature, analog coverage is also collected at the end of the regression.

Successful top level mixed signal verification has been done on a single buck boost converter.  Five Verifer views are used. A total of 150 regression test cases are built. Gate level simulations (GLS) are performed with parasitic back-annotation. Code coverage data are collected at the end of regression.

Today's chip level simulations utilize more RNM/DMS in addition to the classical DV/AMS to get enough verification coverage within the project timescales. Devices have become more complex meaning RNM/DMS is the only way to verify the system or device in any reasonable timescale to get the product to market. RNM/DMS techniques have expanded enough to model analogue blocks at a reasonable level, for example the User-Defined-NetType introduced in SV-2012 that enabled Cadence to create its enet. A key goal for most companies is to merge the two testbenches (DMS/AMS) and verification framework into one setup, of course to save money! A Unified Testbench (UTB) for mixed signal devices is required meaning that a majority of the information about the hierarchy needs to come from the schematic capture environment. This presentation will show how a UTB can be done in Virtuoso.

The UNL netlister is well known as the Cadence’s bespoke AMS netlister that works in harmony with Cadence’s simulator to enable an array of complex design configurations to simulate. There should be no under estimated in the complexity given language limitations and numerous use-case models.. To leverage the unified testbench and allow that netlister to work with many other tools other than simulator a LRM compliant SystemVerilog netlister was required. Cadence has provided this in the from of the Virtuoso SV Netlister VSVN (AKA SV-UNL) . Dialog has worked directly with R&D in making sure the VSVN is LRM complaint and has the same quality as the AMS-UNL netlister.  (Dialog’s contact with R&D is an Accellera committee member for Verilog languages.)

22FDX is the technology of choice for modern day IoT, RF, 5G, mmWave applications only possible due to its first in class technology integration capabilities. These technology integrations require seamless design and analysis capabilities between analog and digital. A qualified Mixed Signal OA (MSOA) database is going to open up a new dimension of design planning and exploration to help designers realize their imagination with the help of best in class PDK offered by GLOBALFOUNDRIES and Mixed Signal flows offered by Cadence Design Systems.

The scope of this paper to show how re-use digital UVM based environments and digital techniques such as SVAs and SV checkers in verifying large complex mixed signal IP by taking advantage of electrical discipline partitioning.

State of the art multi standard high speed SerDes IP designs contains several power and functional modes supporting a wide field of applications.

Process corner, supply and system effects are handled by complex calibration loops controlled via FSM through the analog domain.

To reduce time consuming re-spins and prototyping, the challenge is to be as near as possible to the silicon effects during pre-silicon debug.

For post silicon debug it is necessary to reproduce and identify serious bug findings during laboratory measurement in the pre-silicon simulation environment.

That leads to high level test benches including complex stimulus to verify the analog behavior.

Using Cadence config view netlisting flow, an exchange of sensitive digital partitions by electrical partitions is possible.

Via electrical and logical Cadence disciplines assignment, electrical islands can be elaborated during elaboration-phase.

While binding user defined connect modules via IE-cards the electrical to digital and digital to electrical domain crossings are well defined at the island borders.

The mixed mode netlists can be used in slightly modified UVM regressions. Those UVM sequences are already available and supported by the digital and model based mixed signal verification.

With this approach debugging and IP verification can be improved while re-using environments through the different disciplines of verification scopes and methodologies.   

This also enables correlation and validation between behavioral models used during digital verification with real analog components (schematics, or extracted layout) used during mixed signal verification.

Introducing inspectAR, the latest in PCB innovations. Our platform uses augmented reality overlays to identify nets, components, and layers to pinpoint problems and cut down rework. Speed up communication between engineers, technicians, and managers. Overlaying every aspect of a design directly onto the circuit board with augmented reality, inspectAR enables interactions with circuits intuitively. Inspect, debug, rework, and assemble PCBs in less time, without mistakes or frustration.

Meeting product deadlines and performance objectives necessitates coordinated planning and optimization of the system fabrics—silicon, package, and PCB. During this co-design activity the designers will face some challenges, including checking the final netlist correctness – which is key to avoid multiple-re-spins of a design.

The Cadence OrbitIO interconnect designer helps the cross-fabric planning and assessment process by unifying silicon, package, and board data in a single canvas environment, enabling engineers to achieve the optimal balance of connectivity for performance, cost, and manufacturability prior to implementation.

This presentation will introduce a new flow for InFO package and will provide insights on design challenges during various stages of a design (package creation, chiplet instances creation and instantiation, driving connectivity with a Verilog netlist, handling of extra package power and ground nets, C4 balls creation, exporting the design to APD+ implementation tool, ECO capabilities, cross platform DRC checks, and WLP netlist correctness validation).

This new flow enables securing the InFO package designs, resulting in fewer iterations and shorter development cycles.

Rigid-Flex PCBs have been used in many modern electronic devices (such as mobile phones, laptops, and wearables, among others), due to their form factor, light weight, and cost-effectiveness. Electromagnetic (EM) analysis of Rigid-Flex PCBs has always been a challenging task for many commercially available 3D numerical solver technologies (FEM and FDTD), due to the complexity in the 3D designs. Much of the complexity comes from bending of the board into small spaces and usage of hatched ground and power planes. In this paper, we first address the key challenges faced by the EM engineers and then propose a novel automated simulation workflow for a fast-to-market product development process. The proposed workflow, utilizing Cadence® Allegro® PCB Editor and Clarity™ 3D Solver, is the first of its kind in the PCB-EM community. Compared to alternative, highly manual processes, this flow is less error prone and very efficient in setting up the design for EM simulation. In addition, it runs faster than the other legacy 3DEM tools in the industry.

Si or SiC based IGBT or MOSFET modules are used in hybrid/electrical vehicles, typically for main traction inverter. Proper PCB layout of IGBT/MOSFET modules during the design phase of modules and proper setup of cooling system during the design of inverter are essential for inverter functionality. In this presentation, inverter development flow, based on usage of Cadence’s  Clarity and Celsius will be demonstrated, with special emphasis on thermal and electrical aspect of design.

Following topics:

- Setup of SystemSI simulation

- Using IBIS-AMI model (example with FPGA)

- Checking the pinning

- Analysis of simulation results

- Eye diagram

- BER with bathtub

- noise bathtub

- S-parameter extraction

- Compare simulated results with measured data

Overview of Cadence Solutions for Addressing 5G RFIC Verification Challenges

Each new generation of mobile phone standards brings new challenges for designers.

Designing to meet the 5G standard is challenging enough; however, once the design is complete, the work to verify that the design complies with standards still remains to be done. In this  discussion, we will explore the methodology and tools that will help you minimize the effect of verification on time to market for your product.

Compact frequency converters for critical communications are used to translate signals such as LTE from standard frequency bands to non-standard bands for transmission over the air.  Although using non-standard bands of operation, it remains vital to achieve regulatory spurious emissions requirements. This presentation describes the design of a frequency converter for time division duplex (TDD) applications that contains internal switches to separate transmit and receive.  Diversity channels are also included.  The compact size and requirements for the five multiple output channels place severe constraints on the physical design, making it critical that components not be over specified, which would result in an oversized design. Consequently, a key part of the design process is the careful system analysis of mixer spurious products, filter passband and rejection characteristics, and amplifier spurious performance.  For this design, a Cadence® AWR® Visual System Simulator™ (VSS) model of the complete system was constructed, which allowed analysis and design of the transmit and receive chains and also predictions of spurious emissions and the effect of external blocking signals on receiver performance. The design process using VSS is reviewed and the results are shared.

5G New Radio (NR) networks represent the next milestone in enhanced mobile communications, targeting more traffic, increased capacity, and reduced latency and energy consumption, made possible through multiple enabling technologies. To achieve 5G NR performance targets, these communication systems must improve spatial efficiency using multiple-in-multiple-out (MIMO) and beam-forming antenna arrays while increasing bandwidth using millimeter-wave (mmWave) spectrum and carrier aggregation (CA) techniques for greater spectral efficiency in the sub-6GHz spectrum band. Each of these technologies present numerous design challenges for engineers developing and integrating components in RF/mmWave front ends.

This presentation examines some of the technical requirements and design challenges in developing high-frequency components supporting 5G NR communications—from beam-steering antenna arrays to mmWave MMIC power amplifiers—using gallium nitride (GaN) semiconductor technology. An overview of typical 5G NR system requirements will be followed by a discussion of how these requirements impact component performance specifications. RF link budget analysis and time-domain analysis will be used to examine bit error rates (BER) and error vector magnitude (EVM) measurements using communication system analysis. Physical implementation of a receiver based on a 45nm complementary metal oxide semiconductor (CMOS) RFIC will also be presented.

Terrestrial television broadcast is a major source of global information dissemination and entertainment. Over the past decade the Doherty power amplifier (PA) has been adopted to increase television transmitter efficiency, thereby reducing operating expenditures. An alternative PA architecture is the digital PA (DPA), which consists of several switching amplifiers controlled in a way to recreate the amplitude modulation of the transmitted signal. A non-isolated transmission line combiner sums the currents from the switching amplifiers, enabling them to load modulate each other and thereby allowing N amplifiers to achieve 2N unique high efficiency output power (POUT) states.

This presentation discusses the development of a 500MHz three-bit proof of concept (PoC) DPA using the Cadence® AWR® Microwave Office® circuit simulator and Broadcom gallium arsenide (GaAs) transistors. The transmission line combiner was optimized with a genetic algorithm to achieve 29.6dBm simulated peak POUT with 50% average efficiency over the seven on-states. The electromagnetic (EM) simulator was used to verify that the resulting printed circuit board (PCB) layout matched the circuit level simulation. From this Gerber files were generated, and the PCB fabricated on a LPKF milling machine. The PoC achieved a peak POUT of 30.3dBm at an average efficiency of 41.3%.

This presentation describes the design of a high power, high efficiency monolithic microwave integrated circuit (MMIC) amplifier developed using Cadence® AWR Design Environment® software and commercially available 0.25µm aluminum gallium nitride (AlGaN)/GaN technology. The upper Ku-band amplifier design uses a moderate power density process with fT = 30GHz, which is a key challenge. The proposed three-stage amplifier delivers 44dBm output power over a frequency range of 13-18GHz. The amplifier has a small signal gain of 24dB and 30% power added efficiency (PAE). The chip size of the design is 4.65mm x 4.6mm.

Artificial Intelligence (AI) design involves integration of various hardware Intellectual Properties (IPs) together at the top level. Hence the design becomes very large and complex. Simulating the design for verification takes huge compute resources and wall clock time. Sometimes it is not possible to simulate such a large design. However, the simulation acceleration and emulation in a single environment is possible using Cadence Palladium Enterprise Emulation Platform emulator and Verification Xccelerator Emulator (VXE) software.

Superlint is fundamental in the developing and in the continuous modification of an IP to avoid dead code, deadlocks/livelocks and arithmetic overflows due to the erasing of obsolete specification. The bugs due to this kind of issues are not easy to find in simulation but this checking is very simple and immediate by using Superlint tool. This saves time for design engineers, verification engineers and avoid bugs that could not be found in dynamic simulation.  For dynamic simulation we have a UVM verification environment in which we have included the Cadence I3C verification IP master in parallel to a custom I3C master developed by our group. This choice is due to the need to have the possibility to check the correctness of the protocol by a third party master (Cadence VIP) and checking some features that are not yet officially released as a specification by MIPI while doing some specific stress test that are not covered in the I3C VIP.

Verifying the absence of System-on-Chip (SoC) deadlocks when integrating a wide variety of IP blocks and interconnect fabrics from various internal and third-party sources is a daunting challenge. Current solutions are typically composed of a combination of technologies such as full-chip simulation, emulation and hardware prototyping. However, deadlock scenarios often occur in rare cases that involve several preconditions occurring in sequence and with specific timing. Consequently, deadlock bugs may only be triggered in extreme corner-case conditions, which are resistant to discovery by traditional methods.  In this paper we present a formal verification solution that exploits the exhaustive nature of formal analysis to overcome this resistance and deliver the confidence required for sign-off.

Verification of a complex SOC today demands the use of Verification IPs from diverse sources. The ability to utilize available verification components and embed them into an existing Verification Environment, which often consist of different languages, is of great importance.  The Accelera UVM-ML Open Architecture provides the ability to assemble and co-simulate components which are written in different languages. Nevertheless, some synchronization aspects as sequences alignment and data transport between those components are left for one's determination.  In this paper, we demonstrate a common case for Multi-language necessity: a SOC written in Specman E environment that utilizes an SV UVM VIP from an external vendor.  In the implementation of this system, we developed a mechanism for data and bi lingual sequence synchronization.

Formal Verification technology allows us to do exhaustive verification with reduced effort in comparison to applying the classic dynamic UVM approach. In this paper we shall share our experience of using Formal Signoff methodology to do verification sign-off of three digital IPs with Formal verification only.

In the Hardware verification world – UVM environments testing RTL - we see continuous increase in the size of designs under test, resulting from the increasing number of modules and sub-systems in each design. The complex designs present new challenges to the verification engineers, and specially to the integrators and tests writers. Two of the main challenges are creating multi-channel stimuli which require synchronization of multiple sub-systems, and ensuring that the testing plans were achieved.  In this paper we will show how one can use Portable Stimulus and testing Standard (PSS) to write tests for HW verification environments (not only SW driven SoCs).