In the basic analog design flow, schematic and layout designers normally communicate with others by schematic notes, emails, and documents. A better method is needed to improve communication between front end and backend engineers to guarantee that all design goals are met. Design Intent, the new feature, provides a method to capture, communicate and trace design goals/intents. It captures all design goals from the schematic and brings them into the layout, keeps a traceable record of implementation status, and also leaves freedom to layout engineers on how the goals be implemented. Design efficiency is improved and quality is guaranteed. This paper introduces Design Intent function and advantages. By studying design methods for improving efficiency and quality during the design cycle, we adopted a better way from Cadence by combining Design Intent with constraint in the analog design flow.

1. New Virtuoso Design Platform for advanced node / heterogeneous system design 2. Advanced design automation features for mixed-signal design • Layout automation & concurrent team design • Simulation driven layout for robust layout design

"Virtuoso ADE Verifier provides a new environment to manage and setup a verification plan for a complete analog and mixed-signal project. It lets you connect multiple implementations (namely Explorer and Assembler maestro cellviews) to the requirements. The Setup Library assistant helps you define the project-specific master setup and ensure that all design blocks adhere to the specified setup. It is available in ADE Assembler and ADE Verifier and performs the tasks like project-specific master setup and save, creating verification spaces, calculate and export analog coverage etc. This paper will share the multi-user regression flow that we adopted based on Cadence ADE Verifier and Setup Library Assistant. Start with DV plan generation, then compare the new Verifier/SLA flow with previous existing flow, and eventually come up with the advantages that this flow brings to us on reliability and flexibility base."

"With the continuous development of semiconductor technology, CMOS devices are becoming more and more complex. In some large-scale designs, the size of the post-simulation netlist often reaches tens of GB or even hundreds of GB. The post-simulation time is usually very long, and the EM/IR analysis of physical structures is even more difficult. Therefore, reducing the post-simulation time of large-scale netlists and seeking a feasible EM/IR analysis solution has become an urgent requirement for each designer. To this end, Cadence launched a new generation of reduction tool "qreduce" in 2019. It can run directly in standalone mode, taking the original netlist as input, and reducing the netlist structure through mathematical algorithms to generate a much smaller netlist that can be used for simulation or EM/IR analysis. Compared with traditional Quantus built-in reduction, it is more flexible, and the supported input types are more abundant and open. In EM/ IR analysis, qreduce can also be used for customized reduction based on selection option, such as specifying partial nets, layers, etc. for reduction, and retaining other original parasitic devices. This not only shortens the simulation time, but also meets the EM/IR demand for IR analysis. Different customization requirements need only reductions based on the same original netlist, eliminating the need for multiple extractions. This topic will introduce the usage of Quantus qreduce first, then use different examples to show the comparison of netlist sizes and simulation run time before and after using Quantus qreduce, also the feasibility of using the selection mode to analyze EMIR for large designs."

The impact of package design on IC performance is getting more and more important, especially for high-performance and high-speed ICs. For example, the coupling interference between die and package and the impact of package to on-chip passive components and critical signals are getting more and more obvious. Traditionally, ICs and packages are designed on different planforms. Nowadays, the disjointed tools are no longer sufficient to address the level of complexities and time-to-market constraints. For chip-centric IC design, we need a system design solution to help build the bridge between IC design and package design, to consider them as a whole during the design period and to realize the electromagnetic (EM) analysis with both IC part and PKG part included, which helps make simulation result as close to real measurement as possible, so that we can improve product success rate and decrease product time-to-market. Using two major flows in the Virtuoso RF Solution, implementation flow with IC/PKG co-design in Virtuoso and an EM analysis flow in Virtuoso with Clarity as EM solver. With the implementation flow, we can import package physical design into the Virtuoso platform easily for IC/package co-design. It helps decrease manual errors due to misunderstandings and improve design efficiency. With the EM analysis flow we realize high-performance and high-capacity EM simulation for both the IC-only case and the IC+PKG case. The Clarity 3D Solver can tackle the most complex EM challenges with gold-standard accuracy, virtually unlimited capacity and excellent simulation performance. With the EM assistant in Virtuoso Layout EXL, we can export all needed IC information into the Clarity GUI easily, we can combine IC part and PKG part in Clarity conveniently, and do EM co-simulation, thus get the coupling interference between IC and PKG with good accuracy. With S-parameter models generated with the Clarity Solver, we can realize system-aware simulation and get a good estimation on critical specs before tapeout.

"FINFET工艺后，随着工艺尺寸不断缩小，CMOS器件建模愈加复杂。进入后版图仿真，寄生效应引起的仿真负荷也愈发巨大。以上两个因素会严重拖累模拟集成电路的仿真速度。 ADLL电路是现代系统时钟系统的重要组成单元。对ADLL的仿真精度要求也随工艺尺寸缩小而愈加严格。在设计ADLL同时，还需要考虑其它不断增多的物理效应，最终留给设计工程师的仿真时间就非常有限了。 Cadence公司提供的全精度模拟仿真器，如Spectre, APS, 其仿真精度一直是业界标准。2019年，Cadence公司推出了新的全精度仿真器SpectreX,它在保持APS同等精度的基础上，能成倍提升仿真速度。这篇文章先介绍SpectreX的简单原理和使用方法，然后重点介绍如何使用SpectreX对ADLL进行精准快速仿真以及对其结果的比较与验证。"

With increasing complexity on advanced node, the SOC design raises big challenge to mixed-signal simulator especially when analog simulator used. In mixed-signal verification, simulation performance of the analog part is usually the bottle neck of full design run time. Lower supply voltage, more corner numbers, more complex device models, dramatically increasing parasitics, which make post-sim of mixed-signal design even more difficult and time-consuming. Comparing with AMS classic flow, the analog solver and digital solver used in AMS-Flexible flow have no version dependence, they can choose any specified version of analog solver and digital solver separately. When we encounter simulation issues, it’s easy to switch simulator version. Besides better flexibility and faster response time, AMS-Flexible flow also provides better simulation performance with less potential issues. Meanwhile, we change analog solver from original APS to SpectreX, which is CADENCE new generation SPICE level analog simulator. Comparing with APS, we observe bigger capacity, better convergence, faster simulation performance, and smaller memory consumption with SpectreX. Three major techniques contribute to benefit of SpectreX mentioned above, optimized modeling MOS devices and interconnects, more efficient memory usage, improved distribution method for multi-CPU scalability. It helps speed up pure analog simulation for analog circuit design, also, it helps speed up mixed-signal simulation accordingly since analog part is usually the bottle neck. With all the reasons mentioned above, AMS-Flexible flow and new SpectreX simulator speed up our mixed-signal simulation on advanced node project, thus improve our design efficiency obviously.

Spectre XPS provides a full solution for advanced-node SRAM with perfect accuracy/performance trade-off, it provides competitive performance even under very tight timing accuracy tolerance such like 3ps/1%. The solution includes a) simulation and characterization for timing/power/leakage b) high yield analysis c) EMIR analysis d) reliability analysis, which are all critical sign-off items. The use model is pure command line, which is friendly and attractive for memory designers. This paper presents the Spectre XPS usage and validation on an advanced-node SRAM project.

The majority of gains in low power occur in the early stages of design – the architecture and microarchitecture level.  Being able to make effective decisions at that stage requires a combination of data and technology to accurately predict how they will translate into the final product, which traditionally has not been possible.  We will give an overview of the Cadence methodology for analyzing and optimizing the design to arrive at the lowest power end product, covering functional verification, high-level synthesis, RTL synthesis, and power estimation/optimization.  This session is followed by a series of deep dives into the individual products and technologies involved.

"By calling the same engines (GigaPlace/GigaOpt/EarlyClockFlow) of Innovus, Genus-iSpatial can achieve a better physical correlation with Innovus. In Unisoc modem case, comparing with the original synthesis flow, Genus-iSpatial can significantly alleviate the congestion problem."

Signoff in the era of “more than Moore”, in which major foundries invest heavily in advanced packaging while keep shrinking transistor size, is full of new challenges which mainly come from the increasing design size and system complexity. In addition, signoff TAT is even requested to be shortened to face intense competition. To meet more stringent signoff requirements, Cadence signoff tools keep innovating in the areas of increasing tool capacity, improving tool scalability, enhancing tool integration to shorten the entire digital flow TAT, and enriching system analysis and signoff solutions. In this presentation, many new solutions will be covered such Voltus-XP, Voltus-XM, Cadence Signoff on Cloud, Innovus-PI, Tempus-PI, Tempus-ECO, Voltus-Sigrity 3DIC Signoff Flow and Voltus-Celsius ET Cosim.

In the chip design at advanced node ,due to the increase of the transistor density and the metal resistance, the probability of IR drop violation increases. How to quickly fix these violations has become a difficult point in the signoff stage . The traditional method analyzes and fix the chip's IR drop violation after the place&route, which requires multiple iterations and is not easy to converge. With the help of Cadence's newly introduced In-design full-flow IR drop fixing and avoidance , the author uses IR aware automatic placement, skewClock IR fixing, and local P/G stripe addition, etc., to avoid and fix the possible IR hot-spot during the placement and routing stage,which effectively prevents the occurrence of IR drop violations, improves the efficiency of IR drop hot spot fix, and greatly accelerate the convergence of static voltage drop and dynamic voltage drop..

Power integration analysis is more and more important in nm level tech node. This is an AI chip of 12nm using 2.5D to integrate HBM with interposer. And full ASIC design contents 450M instance excluding fillers and near 10B PG nodes. It is a huge and complex simulation work for IR analysis. Besides that, we add interposer design and package model both net-base and pin-base to co-simulation to check IR of full system. Cadence Voltus XP technology provide a fully complete flow and high capacity engine. With Voltus XP and multi-die feature, we do static IR and dynamic IR analyses of mix-mode with both vector-less and vector-base. Advanced features 3D-IC enable multi-die analysis with interposer and package together. Voltus XP technology helps to do parallel computing which accelerates run time to finish dynamic rail simulation in 1 day. Getting benefit by this total solution, we verified the whole chip design IR status and achieved signoff criteria.

Performance and power are more and more important on advanced node, while they are tradeoff factor.To achieve higher performance, we need calculate power and whole system IR accurately. Our target is to find a reasonable solution for signoff and silicon power/IR drop correlation when the conditions are different. Voltus static power analysis mode with the peak power vector from silicon test patten can get more accurate power range. It's very important for power forecast on early stage. More performance margin can be released for design. Co-analysis flow on Voltus and Sigrity can help to get a good trend prediction on whole system IR drop..

At the center of the Cadence digital full flow solution, the Innovus implementation tool continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this session Cadence will share the latest Innovus 20.1 release and 2020 roadmap technology highlights. Topics such as physically aware logic restructuring, advanced hierarchy flows, and machine learning will be discussed, all resulting in improved power, performance and area (PPA). Attend this session to learn what the next phase of Innovus Innovation delivers as part of Cadence digital full flow

"Chip comes to be larger and complicated in advanced technology. Chip designer faces more challenge to signoff chip with high quality in short design cycle. Cadence Stylus provides platform to implement chip from RTL to signoff in a common user interface and unified metric capturing and reporting. In this paper, chip implementation method with Cadence Stylus is introduced. We originally implement our chip (21 million gatecount ARM core design) with tradition Cadence flow, that is Genus 18.14 + Innovus 16.20 + Tempus 15.23. When it is immigrated to Cadence Stylus flow, implementation process runs more smoothly and efficiently, while at same time, get better design result. This paper firstly makes introduction and gives result data of tradition flow. Then Stylus migration method is introduced to stitch original separated flow into one common platform. After that, Stylus unified metric report method is introduced, and compares with original design. Finally Stylus best practice experience and user benefit are presented. For our chip, Stylus platform improves more than 15% design quality and reduces 30% total run time..

Based on the company’s projects, this paper completed a back-end design of a sub-module of a Samsung 14nm high-performance graphics chip. The final total instance is almost 15million. The design difficulties of the block is not only come from the runtime but also the placement congestion and clock qulity. The paper mainly study the congestion optimization methods in place stage and compares different strategies of clock tree synthesis in cts stage. The results show that the congestion has been significantly optimized, the overflow is reduced by 3.99%H 1.36%V to 0.30%H 0.33%V. And for the cts qulity, the clock latency reduced from 2.5ns to 1.8ns in ss125rcworst corner, the clock skew reduced from 323ps to 167ps in ss125rcworst corner. By optimizing the power mesh structure and clock tree structure, the problem of routing congestion is finally solved, and realized the timing closure.

Along with the advancement of IC process, the timing analysis is more and more complex and it needs dozens of scenarios for timing optimization during the backend flow. To improve flow runtime and save memory, we use linear regression method to determine which scenario could be covered by other scenario and get a optimal scenarios combination recipe for innovus flow.

在先进工艺节点下，随着设计规模越来越大，时钟频率越来越高以及时钟结构越来越复杂，愈发的发现最终整个设计收敛对于时钟质量的依赖越来越明显。针对如多输入动态mux复杂时钟，IP模块多内部输出时钟等复杂的时钟结构，采用分析时钟框图及基于Innovus工具从网表中提取时钟结构的分析方式进行时钟结构上的详细梳理，提出针对时钟结构分析及clock spec的优化方法。同时在一个超大规模的16nm top design上基于优化后的clock spec进行CTS，并结合multi-tap的clock tree做法，从得到的结果可以发现在run time，clock latency等方面都有较大的提升，能够满足计算条件下的时钟长度等要求，有效避免block接口的时序冲突。

规模日益增大，频率不断增加的高性能CPU设计，在7nm及更先进的工艺节点下设计数据量和复杂度陡增。机器学习是目前计算机相关领域中最热门，应用前景最广泛的技术之一。Cadence innovus的机器学习方案是在工具中内置机器学习算法，通过对设计数据进行学习仿真，建立机器学习模型，从而提升设计性能。建立了一个自动化的机器学习物理设计实现流程来提升CPU性能。详细分析了使用机器学习物理设计流程前后时序、功耗、布线等设计指标的变化，最后又对其他两个高频模块使用机器学习物理设计流程，并进行了较为全面的比较分析，从而明确，使用机器学习物理设计流程后芯片的PPA(Performance、Power、Area)可得到很大的优化和提升。实例结果表明，在7nm工艺下，使用Innovus机器学习物理设计流程后，CPU可实现setup时序优化56.3%，hold时序优化35.64%，功耗优化1.77%，线长优化1.56%。

As design complexity increases, along with time-to-market pressure, the cost of bug-escape at different stage of design and verification also increase. In order to keep up with trend, it is very important to maximize verification throughput. In order to achieve optimal verification throughput, we not only need to use state-of-the-art technologies, we also need a full verification flow that utilize the optimal solution at the right time. Here we will explore the different solutions that address the challenges at different project timing as well as different abstraction-levels.

"UVM is becoming the most popular methodology in block level even SoC level simulation. But existing UVM verification practices do not take the advantage of the commonality between the runs.  The same initialize pahses consumes plenty of time and memories.  If there is an error to debug, it can lead many wasted simulation cycles in duplicated regression runs.
In this paper, we take Cadence Save/Restart and dynamic test as example to investigate a solution to save initialization phases, reuse snapshot to run new sequences in NXP UVM environment. We also analyze the limitation of these flows and expect the advanced features from Cadence."

Growing design size and complexity exerts enormous pressure on the verification deadline. Time-To-Market being a critical factor, DV Engineers are often left wondering “What more can I do to make these tests execute faster?” to shorten the verification cycle. This paper gives insight to some of the methodologies supported by Cadence Xcelium simulator to reduce (re-) compilation, (re-) elaboration and simulation time with minimal effort, resources and little to no changes the existing Testbench. These performance improvement methodologies were selectively experimented on Proj1, Proj2, Proj3 and Proj4 and the encouraging results are shared in this paper.

As the design becomes more and more complicated, it is common practice to construct the model first and then develop the design based on the model. It raises the new topic that how to verify the design against the model. In this paper, we will first present the legacy flow of the MATLAB modeling verification and its limitation. Then we will discuss the different solutions provided by HDL Verifier and the co-operation with the Cadence simulator. And we will also show the structure improvement we did in the project against the standard flow.

简单介绍formal验证的背景，针对现有项目进行分析，并表达在验证过程中的想法总结。

本场直播将介绍Cadence的Indago调试平台, Indago采用现代和创新性的调试概念，如自动根源分析(RCA)，高级数据探索，Smartlog，Signal搜索等技术加速您的验证调试，效率提升50%

介绍人工智能技术在终端设备上的应用及其对AI处理器的需求，并从硬件架构和软件生态两方面介绍cadence新一代专用AI处理器IP - DNA150

视频将向大家介绍Cadence IP研发团队，以及Cadence完整的IP解决方案。同时，视频还将与大家分享最新的行业趋势，以及Cadence在行业中领先的技术和产品资讯。在这个视频中您还将了解到Cadence的本土化策略，Cadence正在将越来越多的先进IP技术和产品移植到国内的先进工艺上。Cadence的技术专家还将重点为您介绍国内先进工艺上的高速DDR IP和SerDes IP解决方案，并进行实验室的现场演示，让您深入的了解Cadence DDR和SerDes的产品和研发情况

Abstract: The level of automation of a vehicle is the key driver of the E/E architecture and the electronic content of a car. It’s obvious that future cars will be equipped with more computing power, AI-based systems, car-to-car communication technology, high-bandwidth Ethernet networks, and digital cockpits. Radar, Lidar and Camera are the key sensors to enable fully autonomous driving. However these sensors still need to be significantly improved in terms of resolution, power consumption, safety, form factor and cost but will also evolve to address new compute architectures. All these new technologies will dramatically increase the complexity of electronic systems which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. As a result, a new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) is needed to process all sensor data and fuse them together to enable vehicles to become “aware” of their surroundings. While some high-end automotive SoCs have been already designed in 7nm some companies are preparing already their next-generation process technology at 5nm. Foundries claim that 5nm provides about 20 percent faster speed or about 40 percent power reduction and is perfectly suited for the next generation of automotive processors. Cadence's Automotive solutions can help you to enable such highly integrated systems that can make cars safer and more reliable. This talk provides an overview on automotive trends and the implications for SoC and System enablement for Sensors and Advanced Driver Assist Systems (ADAS).

Overview of the Allegro Data-Driven Platform for System design, and the updates to the solution available in the latest Allegro 17.4.1 release.

如何在设计阶段基于BUMP的排布，PCB的设计情况。使用OrbitIO工具，在一个设计界面中进行封装的Ball Map的设计优化与考量。

With the rapid development of electronic technology, in order to meet the needs of high-bandwidth storage applications, the data access storage rate is getting higher and higher, and the interconnect density of PCB traces is also getting larger and larger. DDR4 is a widely used and fast parallel memory interconnect technology in the memory field. The operating voltage has dropped to 1.2V, and the accompanying signal rise and fall time has been reduced to the order of one hundred picoseconds. DDR trace crosstalk cannot be ignored. . An effective way to reduce crosstalk is to ensure that the DDR4 signal has a proper reflow plane. In this paper, the DDR4 signal line of a PCB is used as the research object. By establishing different PCB stack up models and using different stack up structures to control the remote reference layer of the DDR4 signal layer, the remote reference and remote reference plus decoupling are analyzed. Capacitance, remote reference and ground shielded DDR4 signal test results. The results show that when the 12V power plane is used as the reflow plane of the DDR4 signal, it will cause crosstalk of the order of tens of mV to the DDR4 signal.

500MHz的时钟信号在测试中出现巨大的回沟，采用理想传输线和 简单分布式模型的仿真方式没能复现出回沟，利用PowerSI 提取的S参数协助复现了该问题。故基于PowerSI进行了一系列优化，解决了此回沟问题。本文将从IBIS模型，布局，布线，上升沿时间，带宽，匹配方法，过孔设计，等长设计等方面进行分析，讲解时钟的设计要点和优化方法。

EDA电子设计工具是解决系统连接复杂性与仿真分析（Simulation）不可或缺的伙伴，从IC载板，各类封装到晶片设计的跨域工程挑战，楷登电子全流程智慧系统设计平台（ISD，Intelligent Design System智能系统设计）产品提供的解决方案，协助客户跨领域，从半导体的奈米，封测的微米与PCB板需要的微/毫米等级的引脚/间距、I / O模型、热与电的设计驱动，并针对支持各种不同技术需求从数字芯片的层次结构（Hierarchical Structure），模拟芯片以及数模混合设计，到系统与模块的整合设计与测试平台设计挑战问题（PCB Load board），如何面对并解决异质整合技术在硅中介层（Silicon Interposer）设计上的困难。 本场内容包括说明楷登电子现有的EDA工具如何有效且完整的来协助客户开发包括5G天线封装（AiP）与HBM等更复杂结构的设计，并与业界先进公司发展Chiplet的功能，同时如何帮助半导体生态系统伙伴，快速适应异质整合市场，协助自己与最终客户有效缩短设计周期，提高设计品质与降低成本。

Sigrity/Clarity technology in 2020 and beyond

As power densities on IC designs continue to increase, controlling temperature on the chip is becoming a major challenge for IC designers. High temperature impacts both the reliability and electrical performance of ICs. Floorplan changes can have a big impact on max chip temperature, designers need a way to accurately perform chip-level thermal analysis to model the thermal impact of floorplan changes. Higher temperature gradients on chip also require accurate analysis to find the right placement of temperature sensors. Today’s advanced applications whether they are in automotive, datacenter, mobile, healthcare or high-performance computing, transient thermal analysis, which is typically not addressed by other tools, is a critical factor in understanding thermal behavior and the impact of dynamic thermal management on performance.

With the continuous increase of data transmission volume and speed in the cloud computing, data center and 5G, the 112G PAM-4 SerDes serial channel will gradually become the key interface for large-scale data transmission and network equipment. The ultra-high datarate brings challenges to the design and simulation of the entire SerDes channel, including but not limited to package substrates, silicon interposers, PCBs, and connectors. The new challenges in design and corresponding strategy will be discussed for high-speed PAM-4 serial link interfaces, and how to use Cadence® Sigrity ™ technology and Cadence® Clarity ™ 3D Solver to address these challenges are covered in this topic.

"JEDEC已经于2018年11月发布了最新的GDDR6标准，DDR5的标准也即将发布。这两种并行总线接口在电气特性上有很多相似之处，相比上一代接口，在速率上实现了翻倍、增强了EQ能力，这些升级不但给仿真方法论和EDA工具带来了很大的挑战，对系统设计的要求也非常高。 本文从工程应用的角度讨论了一种GDDR6的仿真方法。文章分为两个部分，第一部分讨论了DDR5/GDDR6的升级给仿真带来的困难，并介绍了一种通道仿真+瞬态仿真的混合仿真方法；第二部分介绍了一个GDDR6实际案例，采用CADENCE的EDA工具完成了系统的仿真设计，分析了GDDR6的设计难点和预期结果。"

"Cadence AWR® Design Environment® Version 15 (V15) offers key new technologies for greater design efficiency and first-pass success to engineering teams developing or integrating III-V and silicon integrated circuits, multi-technology modules, and printed circuit board assemblies for 5G, automotive, and aerospace/defense applications. The new and improved features offer greater design support for RF/microwave engineers developing power amplifiers, antenna and phased array systems, RF PCBs, modules and sub-systems. Engineering productivity is improved with: .new analyses and synthesis .faster, high-capacity EM simulation technologies .time-saving design automation .5G New Radio (NR) compliant test benches".

5G, IoT, automotive and datacenter is rapidly expanding need for simulation. The form factor is shrunk, and design complexity is increased while the signal transmission speed is increased continuously. To meet time to market with good accurate sign-off flow, more and more design requires true 3D electromagnetic modeling. Cadence Clarity 3D is an innovative full wave solver providing accurate and fast modeling for chip, package, connector and system board. A massive parallel computation technology can leverage existing machine resource and less memory to complete a complicated model extraction. Allegro and Clarity integration provides a very efficient and accurate model for rigid-flex board designs.

With AI and machine learning rapidly growing in recent days, HBM technology with much higher memory bandwidth is required for parallel computation applications. For AI chip designers, they are facing much more challenges in high power consumption, high density, limited space, high signal quality and power noise performance etc. This paper firstly discusses one large-scale AI interposer design and its modeling techniques. Then the extracted models are used in the system-level HBM simulation, several new methodologies are implemented to predict the critical power noise. Finally, the simulated signal and power performance correlates well with the HBM lab measurement and vendor’s reference data.

Nowadays high end applications, such as AI, servers, storages, networks etc, which require high speed bandwidth and extreme performance. Process evolution becoming more and more difficult, 2.5D&3DIC solution extend Moore Law and fits well for exabytes data processing,for example TSMC CoWos 2.5D IC solution.There are many challenges need to overcome, 3D structure is much more complexity, difficult to modeling,analyze, verify and sign-off. Among in those challenges ,Power and Signal Integrity analysis for 2.5D&3D IC system might be most difficult.
Different from the traditional 2D system PI&SI analysis, this paper will show: New signal and Power Integrity analysis method for 2.5D CoWos &3DIC design were introduced. This SI/PI solution base on TSMC 2.5D CoWos design, including HBM interposer+PKG+PCB signal and power model building and multiple channel eye diagram and timing analysis,which using Cadence solution with Clarity3D,PowerSI and SystemSI tools. Fast and Accurate modeling and simulating methodology help to verify 2.5D CoWos&3DIC design quality and time to tape-out.

Conformal antennas used in modern mobile platforms require in-situ tuning and optimization. The antenna performance and frequency response are significantly impacted by the various elements of the platform including the case, display, and other metallic structure to the antenna. Since the versatile of modern mobile devices, the components and structures are ultimately close to the antenna. The full-wave 3D solvers must be utilized to accurately model in-situ antenna response prior to design signoff. Beyond the requirement for in-situ antenna analysis, density of modern mobile designs force engineers to also simulate antenna de-sense response. RF and high-speed digital signals radiating off boards, packages, cables, and connecters inside the mobile device couple to the antenna and can significantly degrade the performance of radio receivers. In this talk, the illustration for Clarity 3D field solver can be utilized to perform efficient and accurate analysis of mobile antennas in-situ, and incorporate radiating boards, package, and connectors to model complex de-sense analysis.

Accompany with 5G development, RF module design will meet more challenge in linearity, power and heat necessary to be successfully in the handset market. How to get efficient and accurate EM model will help designer to shorten the design cycle and bring to market better products with less risk. This presentation will introduce a new RF solution -EMX to overcome the upcoming 5G’s difficulty.

As design complexity increases, along with time-to-market pressure, the cost of bug-escape at different stage of design and verification also increase. In order to keep up with trend, it is very important to maximize verification throughput. In order to achieve optimal verification throughput, we not only need to use state-of-the-art technologies, we also need a full verification flow that utilize the optimal solution at the right time. Here we will explore the different solutions that address the challenges at different project timing as well as different abstraction-levels.

在一个多核的SOC系统当中，不同的处理器核对内存空间和设备空间进行着大量的数据读写操作，单一的验证环境更多的集中于控制流方面，而包含数据正确性检查的验证由于控制流程复杂、数据量大等问题而难以实现。针对这一问题，本文基于Cadence公司提供CHI VIP、AXI VIP和IVD VIP，实现了多核环境下的系统级数据一致性验证。本文所设计的验证平台中采用CHI VIP通过笔者开发的CHI协议转换桥发出访存请求，并由AXI VIP收集到达主存的数据，最后由IVD VIP对CHI端口的请求数据与AXI端口的访存数据进行比较，以验证系统级数据一致性的正确性，实现在较高抽象层次上的激励产生和响应检查，在子系统级及系统级可以进行快速而高效的数据一致性验证，具有验证环境搭建快速和功能点覆盖完备的优点。

性能分析是架构设计的重要因素，针对不同架构迭代能迅速提供性能分析的环境并得到关键路径的性能统计数据是性能分析的关键。Cadence IWB (Interconnect workbench)可以提供自动的测试环境构建，regression和性能数据统计，提供图形界面对收集到的性能指标进行分析，实现了可以快速迭代，找到最佳性能架构的流程。本文给出了针对DDR子系统的IWB实现流程，包括架构的输入(excel输入)，自动产生的测试环境介绍，regression的运行，以及最终收集的性能结果和报告。针对DDR子系统来说，从master到DDR路径上不同层级性能分析和优化对整个架构设计极其重要，但是由于Cadence IWB自动测试环境目前还不支持multi-layer结构，于是我们采用了一种巧妙的方式实现了multi-layer性能分析—— 使用Out of Module Reference (OOMR)方式产生testbench并仿真测试，也即是对路径上的模块不直接通过IWB来自动产生testbench，使用平行顶部的设计，对关注层级的interface手动连接到顶部testbench中，实现IWB在分析整体性能的同时还能对关注层级的性能进行分析报告。

随着芯片设计复杂度的增加，裸机系统级验证对于及早发现设计缺陷越来越重要。在PCI-E控制器设计验证过程中，常用的传统验证方法有两种：i）在子系统级搭建UVM环境，编写定向激励进行仿真验证，其缺陷在于覆盖的功能点有限且仿真效率较低；ii）在系统级启动操作系统，然后再进行外设测试，其缺陷在于调试过程复杂且定位问题困难。为解决上述问题，本文使用Cadence公司的Perspec及相关VIP工具，通过生成能够运行在裸机系统级的随机激励来对PCI-E控制器进行充分验证。可实现双向通路访存、DMA Cache 一致性、中断测试、压力测试等多种场景的随机激励生成，解决了裸机激励缺失的问题；此外，该工具所产生的裸机激励还可以加载到加速器平台进行仿真，提高了仿真速度；同时，由于仿真在裸机系统级运行，调试过程简单，可实现问题的快速定位。最后，实际应用表明这一方法极大地提高了PCI-E接口控制器仿真验证效率，相关实施原理可应用于其他接口的裸机系统级验证。

PCIe接口是处理器芯片上使用非常广泛的一种高速接口。通过PCIe接口，处理器可以与多种高速外部设备进行连接，完成不同场景的应用。因此，在处理器的RTL级设计开发阶段，对PCIe接口设计的验证显得尤为重要，需要通过不同的验证平台保证PCIe接口设计的功能正确性和性能稳定性。本文对基于Cadence 硬件仿真加速器创建处理器设计的PCIE接口验证平台的方法进行探究，同时结合实际项目完成该方法的实施，并完成该种验证解决方案的总结。

This speech shared how Microsoft helped the digital transformation of the chip industry through cloud technology. Especially by choosing suitable computing power, optimizing storage solutions, and customized self-developed tools to balance the performance, price, and ease of use of EDA tools in the cloud process. At the same time, he also shared how Microsoft and the ecosystem can build a friendly cloud solution, helping large chip design manufacturers, manufacturers, or emerging small and medium entrepreneurial companies to find their own solutions.

The cloud of electronic design is a new industry trend that has recently emerged and developed rapidly. Why did it arise? What can you bring to you? How to solve the security problem? We invited the industry's top cloud service providers and Foundry factories to share their experience with you. In addition, Cadence started the early attempts of electronic design on the cloud ten years ago (hosted services), and today it has formed a complete solution on the cloud, serving more than 100 customers. In China, we have also implemented a model of local team building, local cloud networking, local customer use, and local team support. Today, Cadence experts will also give special presentations and demonstrations.

With the rapid growth in design complexity and demands of leading process nodes, the compute and infrastructure needs for next-generation designs pose new, daunting challenges. That’s why every high-performance team is looking at Cloud with great interest. The scalability and agility offered by cloud addresses many of the gaps in design infrastructure. However, transitioning to cloud requires thoughtful decisions about cloud architecture, data management, infrastructure setup, security, to name a few.

In this session, we will discuss the pros and cons of various cloud architectures, their suitability for design flows and IT needs for successful cloud transition. We will also describe the Cadence Cloud solutions used by over 100 customers to successfully embrace cloud for their production designs

AWS semiconductor design customers can quickly launch a secure IC/SOC development environment, allowing teams from small and large fabless semiconductor companies, and their external collaborators, to reduce time to market and speed the semiconductor development process. In this presentation we will guide you through the process of scaling out your workflows on AWS, from RTL to Silicon. With a step by step walk through of an AWS reference architecture diagram, we'll provide guidance for connections, infrastructure for the design environment, data transfer, data analytics, and how to enable collaboration across the semiconductor ecosystem. Additionally, we provide examples and resources that can be leveraged to build out your own environments on AWS.