Days-to-Minutes Productivity Through Automation

The Cadence Virtuoso Layout Suite, part of the Virtuoso Studio, provides an integrated place-and-route (P&R) solution that cuts down custom layout implementation from days to minutes. Enhanced layout productivity is achieved through best-in-class placement and routing engines for device, standard cell, memory, and chip assembly design styles. With the automation engines connected through the unified, easy-to-use interface in the familiar Virtuoso Layout Suite, you can build a seamless P&R flow according to your design needs to achieve the best-quality results and accelerate time to results.

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Easy-to-Use Integrated P&R Technologies Accelerate Custom Layout Creation

High-Quality Results

Switch to appropriate automation engines according to design style

Flexible Design Flow

Configure the integrated P&R flow using presets

Better User Experience

Familiar use model to drive automated layout creation graphically without any scripting

Large Capacity

Methodologies to tackle process node complexities

Multi-Pronged Approach, Right Technology for the Job

  • Non-uniform gridded automatic placer for advanced-node structured device layout
  • Track-based device-level automatic router for custom/analog device-level layout
  • Tight integration of best-in-class GigaPlace and NanoRoute engines for automated implementation of standard cell-based layout
  • Advanced layout finishing automation for leading process nodes down to 2nm
  • Spine-style specialty routing of high-capacity memory layout
  • Spreadsheet-style user interface for easy routing constraint management
  • Results browser with powerful query and filters for efficient routing analysis
  • Constraint checkers to detect design intent violations from ECO

Device-Level Layout 

Improved automated placement and routing solution in Virtuoso Studio enables you to easily create DRC-correct analog and custom digital device-level layouts on advanced-process nodes. Intelligent device grouping, fine-tuned controls for device array placement, row-based as well as non-uniform grid-based device snapping, and advanced cell fill drives the automated creation of symmetric analog device placement.

Automated routing on width spacing-based track patterns with support for mesh routing structures alleviates complex wiring troubles for a large number of series/parallel devices in FinFET process technology.

Standard Cell

The industry-leading GigaPlace and NanoRoute engines from Cadence’s Innovus Implementation System are integrated seamlessly into the Virtuoso Layout Suite to provide highly efficient standard cell P&R automation for advanced-node digital blocks in your mixed-signal designs.

Use these engines within your familiar GUI-driven use model to achieve digital block implementation without any hassles. You can get quick routing results through intelligent data abstraction and high-quality results by preventing mistakes through powerful pre-route checkers.

Memory Design

Structured routing of thousands of addresses and data lines needs specialized routing algorithms. The patented routing technologies included in the Cadence Unity Custom Digital Router address the precision-routing challenges in memory designs, due to extreme aspect ratios, minimal routing layers, and complex floorplans. The Unity Custom Digital Router includes step-by-step guided routing flows with a graphical user interface (GUI) showing each step. The customizable guided flow informs you of the progress through the flow and the prerequisites for each step, empowering you to oversee the automation and generate handcrafted-quality routing results in minutes.

Chip Assembly

Integrated into a unified use model, Virtuoso Layout Suite offers various types of assisted and automatic block P&R. You can choose the analog auto placer and incremental placer from Virtuoso Studio or mixed placer technology from the Innovus Implementation System.

Virtuoso Studio reintroduces the enhanced Virtuoso Chip Assembly Router in Virtuoso Layout Suite to solve your block-level routing challenges. The router exhibits fast time-to-results and improved quality-of-results for track-based layouts in advanced process nodes as well as non-track-based layouts mature process nodes.

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