Virtuoso Layout Suite

Group Array

Group Array helps lay out arrays of uniform objects, including instances, vias, and routing shapes. It supports instances with different connectivity to overcome the limitations of schematic versus layout correspondence when using mosaics. Clones can also be generated as Group Arrays, providing quick placement of repeated layout structures. Routing mesh and arrays of vias can be handled without creating extra levels of hierarchy in the layout.

ModGens

Common-centroid device arrays for symmetric placement of matching-critical circuits can be created using module generators (ModGens). Predefined patterns quicken the array definition, and the symbolic placement pattern editor with an intuitive graphical use model provides complete user control.

Symbolic placement of devices

Symbolic placement of devices is a new innovative transistor-level placement-planning environment that combines symbolic display, row-based placement, smart editing features, and smart flight lines for visualizing routing complexity. Using the smart symbolic display, you can focus on the most relevant information needed to complete the task while abstracting unneeded data elements from the layout canvas. This placement methodology can save up to 50% of the layout time.

Advanced assisted wire editing

Virtuoso Layout Suite XL has a robust set of constraint-/design-rule–driven assisted wire-editing capabilities. This comprehensive, interactive wire editor is natively integrated and supports advanced-process nodes along with an array of custom specialty routing constraints such as bus/bundle and shielding. These features are productivity enablers for almost all layout engineers, who no longer need to generate complicated scripts to get desired results.

Auto Via

Having the appropriate via at the metal intersections impacts manufacturability and yield. With the plethora of complex metal-width and color-dependent design rules in modern processes, remembering the right via at each intersection is nearly impossible. The Auto Via functionality in Virtuoso Layout Suite XL comes in handy with its DRC awareness and context sensitivity to insert the perfect vias. The Auto Via assistant helps check the robustness of the mesh routing structures by identifying missing vias at the metal overlaps and indicating debug scenarios where vias can’t be inserted due to DRC violations.

Signoff quality in-design DRC

Accurate DRC during layout editing is vital for faster layout completion. A fast checker based on rules in the OpenAccess technology file helps in wire editing and via creation. A full signoff quality checker is available in the layout through the integration of the Pegasus Verification System into Virtuoso Studio. Using the Cadence Physical Verification System (PVS) or Pegasus DRC runset, you can perform design rule checking on partial layout in-design for quick turnaround time and create a high-quality layout, thereby avoiding any late surprises during the signoff stage.

Application Readiness Checker cockpit

Different design flows need different levels of XL compliance. The Application Readiness Checker cockpit provides a unified interface for managing the checks for all applications, running the checkers, and updating the layout to fix the errors flagged by the checks. For example, checking the layout against the source schematic and updating components and nets to correct mismatches can be done from the Application Readiness Checker cockpit. The cockpit also has the ability to fix schematic versus layout correspondence of an LVS-clean hierarchical layout using the LVS result from the Pegasus Verification System.

Cross-section viewer

To analyze the technology process or debug connectivity issues, users can visualize a cross-section of a specific layout design area using the cross-section viewer. The cross-section will be displayed dynamically in a floating widget following the cursor. It can also be displayed using an assistant and frozen to cross-select. The cross-section helps understand the layer stack present at a user-specified location on the layout and identify opens or shorts.

Design intents

Virtuoso Studio delivers an innovative methodology for managing designer intentions across front-to-back custom design implementation. The circuit designer can specify the requirements through design intents in the Virtuoso Schematic Editor. The design intents are transferred automatically to the layout editor and converted to constraints for the automated place-and-route flow. The layout designer can also manually create the layout by following the design intents and then communicate to the circuit designer that the requirements are satisfied.

Design Review Editor

Information from peer review of the layout can be captured in the design itself using the Design Review Editor in Virtuoso Layout Suite. The tool enables the reviewer to conduct a systematic design review by following a customized checklist and flagging the defect in the layout, which the reviewee can refer to and resolve.

Capture and Replay

The Capture and Replay assistant lets you record a series of actions that can be saved and replayed later to automate repetitive tasks without any scripting language expertise. The capture step defines the layout editing actions that you need to perform and saves it as a macro. The assistant shows the various captured macros and lets you run any of them at the replay step. A single click to perform a series of actions boosts layout productivity dramatically.

Copy route

Copy route allows easy routing of large bus signals over a long distance using a single bus bit as a topology reference. From the reference, the remaining bus bits can be created automatically with options to change the wire width, layer, and spacing as needed. This eases the addition of bus bits to an already routed bus. The Preview mode can be used to detect obstacles to the bus routing and move them out to create space for the wires.

Automated device placement

Virtuoso Layout Suite EXL supports automated structured device placement based on rows or non-uniform grids for advanced-process nodes. The guided flow in the Auto-Place-and-Route assistant helps the user set up the design, create placement grids, automatically create device grouping constraints, generate the device placement, and automatically insert filler cells and guard rings to complete the placement of device-level designs.

Figure 2: Automated Device Placement

Virtuoso custom-digital placer

The Virtuoso custom-digital placer automatically places standard-cell-based designs using traditional row-based methods. This placer, coupled with our space-based router, can be used to rapidly implement custom digital blocks within the Virtuoso environment on mature nodes.

In-design electrical awareness functions

Monitoring electrical issues as the layout is created is essential to avoid multiple design iterations and “overdesign.” With the electrical-aware design methodology, Virtuoso Layout Suite EXL provides capabilities to analyze the parasitics of the interconnects and size the wires correctly without excess parasitics. The tool provides in-design fast capacitance, point-to-point resistance extraction, and parasitic visualization on the layout canvas. Electrical constraints can be checked automatically, and suggestions can be provided to fix the violations. In-design EM-IR analysis can be performed using the terminal currents available from the simulation results stored in the maestro cell view in Virtuoso ADE Suite. The tight coupling of Virtuoso Layout Suite and Virtuoso ADE Suite enables feedback of extracted parasitics from partial layouts to the simulator giving early feedback on the impact of the layout effects on the design performance. This shortens the loop and leads to faster design closure.

Simulation-driven routing

For performance and quality critical blocks, nets in the layout must be routed carefully to satisfy the electromigration constraints. With simulation-driven routing, when the user does interactive routing, the tool automatically looks up the current sources and sinks on the net and calculates the required width of the wire, the number of parallel wires, and the right vias to meet the electromigration rules. The automatic twig generation feature simplifies the interactive mesh routing.