Fast and Accurate Analysis and Debug of Rare Design Failures for Complex I/O, AMS and RF Blocks, Memories, Bit and Standard Cells

The Cadence Spectre FMC Analysis enables fast and comprehensive design space exploration using Monte Carlo simulations of complex analog, RF, I/O, mixed-signal blocks, memories, standard cells, and bit cells while maintaining necessary statistical accuracy. It works with the Spectre X and Spectre APS Simulators and allows you to distribute Monte Carlo simulation workloads to increase throughput. Read datasheet.

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Spectre FMC Analysis diagram

Avoid Expensive Design Rework by Meeting 3- to 6+-Sigma Yield Requirements While Minimizing Simulation Cost

Accuracy

Provides right balance between accuracy and verification throughput using ML and advanced statistics-based accurate estimation of worst-case samples and yield

Throughput

Orders of magnitude speedup versus brute-force Monte Carlo analysis by minimizing the number of samples needed for accurate high-sigma analysis

Scalability

Offers increased scalability through massively parallel distributed processing capability, scaling up to thousands of cores on a compute farm or on the cloud

Ease of Use

Intuitive use model and fast Monte Carlo analysis activated through a simple switch, providing consolidated results for further analysis and debugging

  • Applicable to 3 - 6σ+ applications: Includes memory/bit/std cells, analog, RF, and I/O blocks
  • Integrates with Cadence characterization and static timing flows
  • Determines design yield with a fixed user-defined simulation cost
  • Supports command line and Virtuoso ADE use models
  • Scales to thousands of cores across compute farm and cloud infrastructure
  • Detailed results include worst-case corners/samples, statistical moments, contribution report on circuit parameters, and QQ plots
  • Quick estimate of design yield before getting into fine-tuned analysis of the worst-case failures through Monte Carlo simulations

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