Broadcom
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Overview
Engineering teams are overloaded and need help to keep up with the ever-increasing demands on chip designs. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, artificial intelligence (AI)-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus will intelligently optimize the design to meet these power, performance, and area (PPA) goals in a completely automated way.
By adopting Cadence Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cadence Cerebrus full-flow reinforcement learning technology and large language model (LLM) capabilities in Cadence.AI Generative AI Platform, engineering team productivity is greatly improved.
Chip design flow from RTL to GDS, automatically optimized for PPA
Engineers can quickly optimize flows for many blocks concurrently and use that knowledge for the next design
Efficient distributed compute AI technology, also enabled for cloud
Designer cockpit allows interactive results analysis, so engineers always have control
Features
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Press Release
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Press Release
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Article
Cadence Generative AI Solution: A Comprehensive Suite for Chip-to-System Design
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