Cadence iPegasus Verification System for Virtuoso Studio

iPegasus DRC

The creation and verification of complex SoCs, particularly at advanced nodes, can be a time-consuming process. iPegasus DRC for Virtuoso Studio improves productivity and delivers instant signoff quality DRC to achieve a higher quality layout to meet overall demand for faster design cycle turnaround time. iPegasus DRC, combined with foundry-certified rule decks, runs the Cadence Pegasus Verification System in an instantaneous interactive real-time mode (iPegasus). It helps to boost productivity and layout quality with in-design signoff physical verification checks.

iPegasus DRC is an in-design DRC tool that can be invoked during layout creation or modification. It uses a signoff DRC rule deck and runs DRC directly on the layout without data translation. iPegasus DRC is an on-demand DRC that allows running design rule checks with five modes ranging from the visible area to a whole cellview. In addition to the area-specific checks, it lets you check the edited portion of the layout through the “Changed Area” option. These modes allow you to invoke DRC at any stage of layout editing or fixing. Further, you can continue layout editing while iPegasus DRC is running. It can operate on the “read-only” cellview, which is very useful when the layout is managed in a version-control environment. iPegasus DRC excludes the run-time overhead introduced by data translation and rules compilation. So, for small blocks or device-level designs, iPegasus DRC is more attractive than its signoff counterpart.

Key features of iPegasus DRC for Virtuoso Studio include:

• Higher performance
• Capability to run DRC on the complete layout as well as specified areas
• Run-time improvement leveraging snapshots for design rule capturing
• One-click access to run the DRC