Maximize Analog Design Yield

The Cadence Virtuoso Variation Option extends the statistical variation and optimization capabilities of Cadence’s Virtuoso ADE Assembler and Verifier tools to allow for more sophisticated design centering and statistical analyses to be performed on any design to enhance overall design robustness and yield, even with advanced-node technology.

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Sophisticated Design Centering and Statistical Analyses for Maximizing Analog Yield

Easy to Use

Choose your statistical or optimization task, specify your target, and press a button

Find Statistical Outliers Quickly

Analyze long tails 4-, 5-, or 6-sigma level fast

Detect Most Influential Devices

Use mismatch and statistical sensitivity analyses on critical devices

Move Easily Between Corners and Statistics

One-step creation of worst-case corners from statistical data saves time

Center New Designs to Specifications

Extensive AI algorithms solve difficult design centering problems

You can use a variety of statistical and optimization methods for most design centering challenges and yield problems common with advanced-node designs.

  • Statistical sample reordering for performance:
    Quickly solves challenges associated with advanced-node 3-sigma design, especially at advanced process nodes or circuits with low Vdd
  • High-yield estimation for 4-, 5-, or 6-sigma analysis:
    Parametric high-yield estimation available in conjunction with the Cadence Spectre X Simulator to find problem samples in long statistical tails that may impact design safety
  • Automated yield improvement flow:
    Automates device size changes to meet all design criteria at the highest possible yield, guiding you on best size choices for highest yield
  • Mismatch contribution analysis:
    Identifies important contributors to mismatch variation for easy modification
  • Design space optimization:
    Extensive AI algorithms tuned for advanced-node designs rapidly re-center designs after process migration while private algorithms can also be integrated

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