Overview
Gold standard for Flash Toggle NAND memory device for your IP, SoC, and system-level design verification.
In production since 2011 for many production designs.
Cadence® Verification IP (VIP) for Toggle NAND is applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification to provide verification of Flash NAND devices using toggle mode DDR 2.0 and above. The VIP for Toggle NAND is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported specification: toggle NAND DDR 2.0 Single-Level-Cell (SLC) and Multi-Level-Cell (MLC) devices as well as Toggle NAND DDR 3.0/4.0 Single-Level-Cell (SLC), Multi-Level-Cell, and Triple-Level-Cell (TLC) devices from Hynix, Samsung, Toshiba, and SanDisk.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
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Speed |
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Bits per Cell |
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Memory Sizes |
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Configurability |
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