Power Optimization

What is Power Optimization, and How Does it Work?

Power optimization is the application of specific design techniques that reduce the power consumption of an electronic device. Power optimizations are generally grouped into optimizations that affect static and dynamic power consumption. Dynamic power is consumed due to switching activity, while static power is consumed when a circuit is powered on but not switching. Power optimizations often adversely impact performance and area; therefore, the practical application of power optimization techniques involves the analysis and tradeoff of power, performance, and area (PPA). The following are two techniques commonly employed in power optimization:

Power Gating

Power gating is conceptually simple and involves inserting design structures that turn off the supply voltage to a circuit during idle periods where the circuit is not in use.

For example, many smartphones contain sensors that detect when the phone is physically close to the user’s head (ear) and automatically shut down the display. In addition to preventing unintended display interactions, this reduces the power consumed by the display and its associated graphics processing.

Some of the more challenging aspects of implementing power gating are determining when a circuit should enter shutdown mode and how to restore the circuit from shutdown to active mode efficiently. This requires a detailed understanding of the circuit’s state (in order to restore the state) and the design of predictive controls that ensure transitions to shutdown mode happen only when this mode is likely to be of sufficient duration, such that the power consumed in shutting down and restoring the device is less than the power saved during the shutdown mode.

Clock Gating

Most digital designs are synchronous, and therefore, have clocks. The clock switches at a particular frequency and data flows from registers through combinational logic between clock edges. Thus, clock edges trigger switching activity and dynamic power is consumed. Similar to power gating, during periods where functions are idle, the clock can be turned off (gated) to eliminate switching activity and the associated dynamic power consumption.

Some challenges associated with implementing power gating involve identifying when functions are idle and managing the timing effects of inserting gates in the clock distribution circuit.

 

Benefits of Power Optimization

Power optimization is now a significant focus of hardware design. Power dissipation affects end-product complexity, cost, and differentiation. With the growth in untethered devices—battery-powered handheld and IoT devices—power optimization has become a critical step in the design flow.

Here are a few benefits of power optimization:

Longer Battery Life

From cell phones to electric vehicles, mobile devices are pervasive, and battery life is often a critical differentiator that can make or break a product’s market success.

Better for Data Center Customers

As more applications move to the cloud and cloud-based applications grow in complexity, employing power-hungry big-data mining and artificial intelligence (AI) workloads, data center power consumption has become a potential barrier to growth.

Reducing data-center power consumption reduces electric utility costs and enables lower-cost cooling techniques (simpler air vs. complex refrigerated liquid cooling).

What Industries Can Benefit from Power Optimization?

Power optimization benefits many industries. From system OEMs to mobile device manufacturers and aerospace companies designing airborne and satellite communications systems, reducing power has become a mission-critical design requirement. Optimizing power yields increase performance per watt and can produce meaningful product differentiation.

These industries include:

Automotive Electric Vehicles (EVs)

While still accounting for a fraction of the overall automotive market, the rapid advances and popularity of EVs suggest this segment will see unabated growth for some time to come. With driving range being one of the dominant factors coloring user experience, power optimization is a crucial design focus, as it translates directly to extended range.

Data Centers

Since power can be 60 – 70% of the total operational cost of Data centers, optimizing power can save millions of dollars. Moreover, reducing data center power consumption opens the door to lower-cost cooling solutions that are also simpler and more reliable resulting in less maintenance-driven downtime.

Mobile Phones

Mobile SOCs typically place the combination of efficiency and performance at the top of the priority list. Mobile users want the best-performing devices but also phones with greater battery life. To accommodate these expectations, engineers must understand and perform various design and optimization techniques for minimizing power consumption and maximizing performance.

High-Performance Computing (HPC)

The current most powerful supercomputer is also at the top of the Green list. Primarily, because the designers have managed to put power optimization principles into practice. They created processors and hardware accelerators that offer both performance and energy efficiency.

Portable Devices

Mobile phones are not the only devices that use batteries and require complex SOCs to function well. Portable battery-powered devices benefit significantly from power optimizations that yield devices with longer battery life and increased performance.

Power Optimization with Cadence Tools

Power optimizations are an integral part of Cadence products spanning C++ to GDSII. Cadence tools comprehensively address power at each stage of the design flow by automated power optimization and analysis. Stratus High-Level Synthesis, Genus Logic Synthesis, Innovus Implementation System, Conformal Low Power, and Joules RTL Power Analysis System are Cadence solutions focusing on power optimization.

Learn more here.