Premier Cadence Events

Keynote1 : Addressing Complexity: Intelligent System Design

Keynote2 : VLSI CAD New Trends & AI Techniques

Advanced-node VLSI design entails significantly complicated and tightened design-rules, so the required quality of result is increasingly difficult to meet. To solve this issue, recently, machine learning (ML) is beginning to have an impact on the VLSI design, predicting results in the early stage or providing optimal solutions with a pre-trained model. In this talk, I will provide a brief summary of recently published works, especially on design automation techniques using CNN, GAN, GCN and reinforcement learning.

AI1 : The Evolution of Sensing, Computing and Architecture Going from ADAS to Automated Driving

The level of automation of a vehicle is the key driver of the E/E architecture and the electronic content of a car. It’s obvious that future cars will be equipped with more computing power, AI-based systems, car-to-car communication technology, high-bandwidth Ethernet networks, and digital cockpits. Radar, Lidar and Camera are the key sensors to enable fully autonomous driving. However these sensors still need to be significantly improved in terms of resolution, power consumption, safety, form factor and cost but will also evolve to address new compute architectures. All these new technologies will dramatically increase the complexity of electronic systems which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. As a result, a new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) is needed to process all sensor data and fuse them together to enable vehicles to become “aware” of their surroundings. While some high-end automotive SoCs have been already designed in 7nm some companies are preparing already their next-generation process technology at 5nm. Foundries claim that 5nm provides about 20 percent faster speed or about 40 percent power reduction and is perfectly suited for the next generation of automotive processors. Cadence's Automotive solutions can help you to enable such highly integrated systems that can make cars safer and more reliable. This talk provides an overview on automotive trends and the implications for SoC and System enablement for Sensors and Advanced Driver Assist Systems (ADAS).

AI2 : Enabling Chips and Systems for Artificial Intelligence

This presentation will introduce the pan-Cadence capabilities enabling the design of systems on chips (SoCs) and systems for artificial intelligence (AI) and machine learning (ML). We will discuss aspects of enabling processor and design IP – the Tensilica DNA 150 – and high-level synthesis to enable optimized circuitry for AI/ML algorithms. Furthermore, we will introduce the requirements for optimized verification of AI/ML designs using the Cadence Verification Suite and its specific optimizations for this category of designs. Advanced node and low power implementation will be key aspects linking verification to SoC implementation and we will discuss specific optimizations offered in Cadence flows. We will close with 3DIC and Chiplet based integration, as well as system analysis aspects.

AI3 : Let’s Talk about Chips (Chiplets) - it's all about D2D

One of the hottest trends in semiconductors today is “chiplets”. It makes sense though…the semiconductor industry has been and is still obsessed by Moore’s Law. As the advancement of the shrinking transistor has slowed (the concern that Moore’s Law is finally coming to an end), the need and desire to develop bigger and larger chips has increased. Talk about moving in opposite direction. So, how do we reconcile this pulling in different directions? Instead of designing these monstrous monolithic chips in a single die, the semiconductor industry is moving to designing and developing chips into smaller and more specialized/optimized blocks (chiplets) that can be “easily” connected to increase computing capability, provide more functionality, increase yields, and leverage multiple process nodes, thus lower costs and preserving the spirit of Moore’s Law.

AI4 : Samsung Advanced Node and Cadence AMS Design Reference Flow

AMS design challenges have significantly increased with complex design specification requirements at advanced CMOS processes. The Samsung 3nm Cadence AMS Design Reference Flow is intended to reducing this design complexity and hence improve design productivity at the 3nm technology nodes by demonstrating to the end users how Samsung foundry PDK’s are well in sync with the latest Cadence Design Tool Suites. Samsung Foundry customers can now take advantage of the most advanced features for circuit design, performance, reliability verification, automated layout, block and chip integrations for custom and digitally-controlled analog designs based on Cadence Virtuoso, ADE and Spectre platforms. In this session, we shall talk about Samsung Cadence AMS Reference Design Flow from schematic to layout verification and the future.

AI5 : Samsung 5LPE High Performance Implementation of Arm Cortex-A78 Processors Using Cadence Digital Full Flow

Samsung have been collaborating with Arm and Cadence to develop an optimized 5nm implementation flow. Samsung will show how the benefits of the 5LPE process node can be utilized to meet high-performance and low-power goals on the latest Arm CPU. Techniques such as Genus/Innovus iSpatial technology, Machine Learning & IR-aware optimization, and final signoff-driven design closure will be discussed, all based on the integrated RTL-to-GDS Cadence physical synthesis flow. This remarkable flow is available to customer as a Rapid Adoption Kit so designers can benefit from Samsung experience.

AI6 : Data-Driven System Design & Analysis

ML1 : Up to 5X More Efficient Regressions with Xcelium Simulation

In this session, we will discuss how to use Xcelium to make randomized regressions faster, how to monitor on-going regressions and identify how randomization influences coverage of the regressions.  Also discussed is how to produce more efficient regression that maintains coverage while reducing simulation cycles up to 5 times. We will examine other potential benefits and real results using Xcelium simulator.

ML2 : Extending Power, Performance and Area (PPA) using Machine Learning

As advanced process nodes become ever smaller, design performance goals always seem to increase, not just for clock frequency, but also power and area. To meet these challenging requirements, Cadence continually develop innovative technologies which will help deliver the latest high performance silicon devices. Machine Learning technology is a good example of a new technique that has enabled designers to push design performance at the latest process nodes. During this presentation Cadence will show how Machine Learning is being used during Innovus Implementation, and as part of Smart Flow Optimization to deliver improved productivity and design performance.

ML3 : EDA and Machine Learning

Electronic Design Automation software has delivered semiconductor design productivity improvements for decades. The next leap in productivity will come from the addition of machine learning techniques to the toolbox of computational software capabilities employed by EDA developers. Recent research and development into machine learning for EDA point to clear patterns for how it impacts EDA tools, flows, and design challenges. This talk will detail the application of machine learning “inside” EDA tools and “outside” tool flows. The convergence of industry trends such as intelligent networks, and intelligent edge and cloud compute along with AI/ML techniques lead to an exciting future for our industry.

ML4 : In-design Signoff Closure from the Innovus™ Cockpit – a Survey Presentation

The digital full flow incorporates unified implementation, timing- and IR-signoff engines. This survey presentation will outline the main benefits of an integrated implementation and signoff environment including improved design power-performance-area and faster time-to-closure. The benefits of machine learning in the context of the closure flow will also be discussed. Learn about the key signoff engines accessible through the Innovus cockpit including: Signoff STA using Tempus™ Timing Signoff Solution Parasitic extraction using Quantus™ Extraction Solution IR drop analysis using Voltus™ IC Power Integrity Solution Physical verification using Pegasus™ Verification System DFM strategies using LDE Electrical Analyzer Agenda: Overview of In-Design signoff from the Innovus cockpit In-Design timing closure using Tempus ECO and Quantus extraction In-Design IR closure using Voltus + Tempus Power Integrity + Tempus ECO In-Design physical verification closure using Pegasus + Quantus + DFM Summary + Q&A

Partner1 : SpectreX Simulator Performance on Samsung Foundry Technology

This portion of talk will take a evaluating Spectre x’ positive effect on design infra reinforcement of Samsung Foundry Technology by Spectre x’ performance and multi-core performance scalability evaluation based on Samsung Foundry Technology using Analog IP, PHY IPs.

Partner2 : Flat Design Signoff with Tempus Distributed-STA

Samsung is in the forefront of developing high functionality complex SoCs. This comes at a cost of high instance count design, which poses a severe challenge for flat timing signoff. Current STA techniques such as flat STA or hierarchical STA solve this problem up to some extent. To solve issues with flat STA, we need to spend $$ to acquire bigger machines and to solve issues with hierarchical STA, we need to compromise with PPA because of inherent pessimism in this solution. DSTA solution from Cadence is a game changing solution. Design team can simply use this method for flat timing signoff with the same accuracy as of STA and using existing smaller machines present in LSF.

RF1 : Overcome RFIC and RF Module Implementation Challenges (Think Outside the Chip)

RF engineers confront a myriad of challenges to bring their designs to life. From the ability to verify a complex 5G or automotive standard, to running electromagnetic (EM) analysis across chip, package, and board, or to simply verifying RF module connectivity, these challenges can overwhelm traditional EDA design flows that are notoriously fragmented by using multiple vendors.

RF2 : How to Efficiently Run Electromagnetic Simulation of Full Circuit Blocks (EMX Simulator)

Electromagnetic (EM) simulation of complex circuit blocks like VCOs can be challenging when you combine active and passive components in a single design. Learn how to perform fast and accurate EM analysis, black-box the active elements, and create multi-port S-parameter models of the interconnect with the Cadence® EMX® 3D Planar Simulator and its parametrizable models for passive components.

RF3 : RF to mmWave Front-End Component Design for 5G NR

5G New Radio (NR) networks represent the next milestone in enhanced mobile communications, targeting more traffic, increased capacity, reduced latency and energy consumption.  To achieve 5G NR performance targets, these communication systems must improve spatial efficiency using multiple-in/multiple-out (MIMO) and beam-forming antenna arrays while adopting more spectrum to increase bandwidth. Learn about design challenges in developing high-frequency components for 5G NR communications - from beam-steering antenna arrays to mmWave MMIC power amplifiers using GaN semiconductor technology. Review typical 5G NR system requirements, learn how they impact component performance specifications and physical implementation with case studies on overcoming design and integration challenges using RF/mmWave simulation software.

RF4 : Design Smarter with AWR Software

Cadence recently launched the AWR Design Environment® V15 version, which includes AWR® Microwave Office® (MWO), AWR Visual System Simulator™ (VSS), and AWR AXIEM® and Analyst ™ electromagnetic (EM) simulators. This new version expands the Cadence software product portfolio and improves the RF/microwave design solution, which can be used for monolithic microwave integrated circuit (MMIC)/RFIC and package/module and PCB design. This version provides key new functions and modules to help customers cope with the increasingly complex 5G, automotive, aerospace and defense applications. V15 improves engineering productivity with new analyses, faster and higher capacity simulation technologies, time-saving design automation, and 5G New Radio (NR)-compliant testbenches that support power amplifier (PA) and antenna/array design, EM modeling, and RF/ microwave integration across heterogenous technologies. Join us for the Cadence AWR Design Environment V15 session! You will learn about the expanded features and capabilities of the AWR Design Environment platform, what’s new in V15, and how to take advantage of the key features and improvements that enhance functionality and improve productivity—from the user environment, to circuit and system simulation, as well as to electromagnetic analysis.

RF5 : Tensilica Radar/Lidar/Communications DSPs

The growth and continue adoption of 5G has driven the increase in the digital signal computational needs for wireless communications. Similarly, in the automotive sector, ADAS, autonomous vehicle, connected vehicle are driving significant growth for sensor signals as well as communications processing. These digital signal processing demands requires specialized DSP to process the massive amount of real-time signal data. The DSP often needs to equip with application-specific optimization and acceleration to achieve the most optimal performance and meeting the processing requirement. Cadence® Tensilica® specializes in domain-specific optimized DSPs and has broad product portfolio to address the needs of the applications requirement. Tensilica® ConnX DSPs for communications applications are capable of addressing the processing needs ranging from low bit rate wireless communications to high data rate of 5G applications. Tensilica® ConnX radar DSPs portfolio provides energy-efficient scalability for sensors ranging from low-cost radar/lidar sensors to high-performance sensors. In this session, we present a high-level overview of one of our ConnX DSPs designed for communications, radar and lidar applications.

RF6 : Hardware/Software Co-Development for 5G/AI/ML

This presentation will outline key challenges for chip and system design for 5G, Artificial Intelligence and Machine Learning technologies that enable the hyperscale computing era. We will discuss requirements of fixed wireless, IoT, mobile and mission critical designs and introduce the Cadence computational software offerings addressing the capacity and performance needs for hardware/software co-development, including emulation, virtual and physical prototyping as well as connections to software debuggers using JTAG and virtual debug connections. Aspects of the strategic partnership between Cadence and Green Hills Software to enable safe an secure software development will also be addressed.

RF7 : Chip-Level Thermal Analysis Using Celsius Thermal Solver

As power densities on IC designs continue to increase, controlling temperature on the chip is becoming a major challenge for IC designers. High temperature impacts both the reliability and electrical performance of ICs. Floorplan changes can have a big impact on max chip temperature, designers need a way to accurately perform chip-level thermal analysis to model the thermal impact of floorplan changes. Higher temperature gradients on chip also require accurate analysis to find the right placement of temperature sensors. Today’s advanced applications whether they are in automotive, datacenter, mobile, healthcare or high-performance computing, transient thermal analysis, which is typically not addressed by other tools, is a critical factor in understanding thermal behavior and the impact of dynamic thermal management on performance.