Leveraging purpose-built cloud infrastructure for EDA simulation to cut down time to market, whereas optimize TCO, increase throughput and Security has become mainstream in global market. In this session we will walk through the latest offering for the EDA building blocks on Azure, business/technical benefit, valuation criteria as well as best practice for running Cadence Spectre X/xCelium/Tempus.

Running EDA jobs on Cloud can be different from on-premises, since it’s possible to run your workloads with the various solutions on Cloud to gain agility, flexibility and productivity. This presentation highlights the best practices and options to optimize EDA workloads on Google Cloud.

Historically, physical verification jobs have been very compute- and memory-intensive. Silicon designers are often resource-challenged to run physical verification on designs that can consume 1000s of CPU cores and require multiple days to complete. The new Pegasus TrueCloud enables designers to run physical verification jobs from on-prem compute resources onto the cloud and has a massively scalable architecture that can reduce design cycle time.

Library characterization for an advanced node design is a compute-intensive task -- ideal for a scalable and flexible cloud. In this presentation, M31 will describe a Library characterization methodology that enabled 5x faster delivery using Liberate on Cadence-managed CloudBurst.

Cadence/M31 IP Solution for Memory and SerDes Interfaces

Designing the Next Ultra-Low-Power Always-On Solution

The Cadence Voltus-XFi Custom Power Integrity Solution is a transistor-level electromigration and IR drop (EM-IR) tool that delivers foundry-supported SPICE-level accuracy for power integrity signoff. EM-IR presents unique challenges at the transistor level, from complex EM rules to the high costs of simulating for current on a large RC network at post-layout. Enabled via an integration with the Cadence Spectre X SPICE Simulator and the Virtuoso Design Platform, the Voltus-XFi solution accelerates power signoff analysis and closure.

In this evaluation, Spectre FX simulates three designs, DDR, PCIE, and PMIC regarding pre-layout, post-layout and mixed-mode simulations respectively. The performance shows 10X+ faster compared to golden runs of Spectre X without accuracy lost.

This speech will introduce which products and processes M31 uses cadence flow, how to use cadence tool with in house developed flow to accelerate the efficiency of reliability verification and inspection, and how to improve the mass production efficiency of products.

The challenges of today's advanced silicon process nodes, as well as stringent performance targets, escalate mixed-signal design complexity. As these designs are created in different abstractions and design flows, exhaustive verification routines are needed to ensure the consistency in functionality and compliance to specifications. In this presentation, MathWorks will present the latest advances in the integrated MATLAB and Virtuoso ADE workflow for data visualization and analysis through the new Mixed-Signal Analyzer (MSA) app to enable seamless data post-processing. We will use a peaking filter/CTLE as an example to demonstrate how we can bring data from Virtuoso in MATLAB, perform a custom analysis such as a rational fit of the peaking filter/CTLE model in the MSA app, generate VerilogA models of the same and bring these models back into Virtuoso to complete a round-trip workflow.

CPU plays a very important role in high performance computing design. Performance, Power, and Area (PPA) all need to push to the design limit. But with the challenging schedule, we don’t have enough time to complete all experiments, and may miss good flow options due to lack of results analysis. Cerebrus AI helps user easy and quickly generate optimal flow reducing time and resources and find solutions human engineers might not naturally try/explore. MediaTek and Cadence close collaboration makes Cerebrus land on production chips and gain great success on CPU PPA improvement.

Global infrastructure is changing rapidly to accommodate growing workloads and increasing performance demands. Arm Neoverse CPUs deliver the speed and energy efficiency needed for the latest infrastructure requirements. As part of designing the next generation Neoverse CPUs, Arm manually develop and fine tune optimized Cadence digital full flow to deliver the aggressive performance and power goals. For the latest 3nm Neoverse CPU, Arm enabled Cadence Cerebrus ML flow optimization which automates the whole process, resulting in better PPA with much less Arm engineering effort. Join this session to learn how Arm are benefiting from automated Cerebrus ML flow optimization for next generation infrastructure CPUs

We are developing a better acceleration design to compute AI algorithms very fast and consume the least resources to fulfill the growing computational complexity of deep learning. As AI models keep evolving rapidly, high-level synthesis allows designers to evaluate the trade-off between performance and resource overhead quickly, and evaluate a variety of microarchitectures at a higher design level, considering the software and hardware integration. As the architecture scales up, there are crucial challenges to exploring the optimized acceleration architecture. We will also share our experiences using high-level synthesis in a human-like robotic arm with intelligent control. Our design platform optimizes the trajectory control of the robot arm with a very efficient hardware architecture. The evaluation can be done in an integrated cyber-physical system of a robot simulator and an electronic system-level platform.

In advanced technology, there are a lot of design issues that need to be solved. At the same time, the power impact is getting more emphasized. Compared to previous generations, the problems of IR drop and EM are becoming more serious. Thus, the accuracy of power simulation directly decides the directions and decisions of physical designs. Considering product competitiveness, we need to get the best results at the shortest amount of time in physical design. From the description above, we know that getting the data completeness in the shortest amount of time for the power analysis are the critical factors in the success of physical designs.

To effectively perform each project and preserve the design experience, especially considering the convergence of the complexity of advanced technology process data and its completeness, Socle has established a through SoC-Imp environment to ensure all the process data are properly set up. Since it’s done automatically, it drastically reduces human resource waste and assure of the accuracy and completeness of the environment and the physical design thoroughness.

Since the major industrial power evaluation tool and physical design tool are Voltus from Cadence, and Innovus, also, from Cadence, respectively. To have more direct design logic for power analysis, we choose Voltus for power analysis, and have integrated Voltus into SoC-ImP to elevate its performance to make sure of the design data completeness and provide an automatic process for each project. Power analysis can be done more efficiently. With more realistic simulation results, it effectively converge the complexity of advanced technology and has the more efficient and smooth physical design process.

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, TSV and Micro-bump insertion, extraction, electrothermal analysis, cross-die STA, and inter-die physical verification . A brief introduction to Cadence® Integrity™ 3D-IC platform will be presented which integrates planning, implementation and analysis to address the new requirements of 3D-IC design and signoff for different packaging styles.

Challenges of NAND Packaging for Capacity & Bandwidth Scaling

5G brings so much data transfer while leading industrial transformation. Not only the user devices need to be upgraded, but equipment in data center have to afford more loading and provide faster data transfer which means higher electrical data rate is considered. In recent three years, with 4-level pulse amplitude modulation (PAM4) has been had high confidence in 50G SerDes/lane and stronger techniques in equalization, it will also be applied to 100G and even future 200G. Meanwhile, big power consumption accompanies because more tap of TXFIR, more stage of CTLE, DFE and FFE. Those high-end equalization induce much power and make network switch system power consumption go to 3000W. Fortunately, we can take the benefit from system in package or system integration technology for relaxing equalizer while reducing power consumption and thermal loading.

In the package design stage, more accurate and fast simulations are important.

How to simulate and analyze more and more differential signal pairs on package at short notice? Cadence Clarity 3D can provide the accurate results efficiently in limited hardware resources. Furthermore, we can use the flexible settings in Clarity 3D to approach the package design.

The Cadence Optimality Intelligent System Explorer is multiphysics optimization software, enabling multidisciplinary analysis and optimization (MDAO) realization of electronic systems. With the increasing complexity of electronic system design and greater performance requirements, Optimality Explorer breaks through the limitations of the conventional human-intensive process by delivering a simulation and analysis workflow that results in the optimal design fast and efficiently. By replacing a traditional interactive flow of design, test, and refine loop, Optimality Explorer, with its artificial intelligence (AI)-driven MDAO technology, results in the optimal system design solution expeditiously and without compromising accuracy.

Thermal management of electronics becomes more critical and complex when resistive losses in PCB and package structures are significant. These resistive losses are also temperature dependent, making electrothermal co-simulation necessary for such designs. In this presentation, we will look at using Celsius for thermal and electrothermal analyses at the PCB level. We will also look at how such designs can be simulated within electronics systems, to capture important system effects (such as airflow within an enclosure) and cooling mechanisms (such as heatsinks and fans).

Phison is the market leader in NAND Flash controllers and applications including USB, SD, eMMC, PATA, SATA, PCIe and UFS. To fulfill the various design requirements and get state-of-arts SOC in advanced process nodes, the design verification becomes one of biggest challenges for chip success and 1st-cut work. Also, in order to get products in time to market, the verification throughput and efficiency are major focus and attentions to improve further.

Cadence verification full flow comprises holistic solution and technologies to achieve and overcome the goal from different angles and realize 

• High Performance & Verification Regression Throughput

• Smart Debug

• Verification IP for New protocols on Phison SOC & IP designs

In this presentation, it will showcase Cadence verification full flow in real Phison SOC projects.

To achieve earlier software engagement for AI/HPC SoC development and validation, GUC proposes a flow to deploy virtual platform into design and verification flow. With this platform, DV team and Software team can exercise application development and software flow in very early stage of project execution. Such that project team can locate/respond architecture flaws and software bugs in timely manner which great contribute to project success.

Two security issues of AI designs will be discussed in this talk. One is about data leakage, especially how to guarantee that the well trained parameters will not be leaked out of the AI accelerator designs by formal verification. The other topic is to discuss the robustness of neural network designs, including what robustness problem is, when we should pay attention to this issue, and how to estimate it with different approaches.

As the world’s leading MCU vendor, Nuvoton provides rich product portfolio from 8051, Cortex-M0/ M23/ M4 to Arm9-based microcontroller, offering numerous parts for selection. In order to develop products with high quality, Nuvoton is always working on improving the verification flow. In this presentation, the speaker will share how Nuvoton leverage Palladium to address the limitation of current verification flow with its huge capacity and rich physical target interfaces. The debugging cycle also get reduced with the help of the strong debugging capability provided by Palladium.

Coverage closure is the TPO signoff criteria for modern ASICs. Design team and Verification teams both took lots of time and effort to reach the coverage goal, and looking for better methodologies and solutions. Randomization of test patterns improves the efficiency of producing many sequences to a design under test. It is especially effective for stressing the design with scenarios that are hard for a human to create directly. While this sounds attractive, it inevitably reduces the understanding of what is going on in the simulation of your tests, which could become problematic when you compose a regression from these tests. A basic question, such as “How many random seeds should be assigned to each test?”, is hard to answer. By extracting knowledge from regression data using machine learning and capturing that knowledge in statistical models. The novel ML capabilities of simulator can help to reach the coverage goal faster and with shorter time.