Mixed-signal fastspice solution is widely adopted in large scale mixed-signal designs for function verification as well as top level co-simulation with digital function blocks. In the past, Cadence did not have complete solution in pure mixed-signal fast spice except Ultrasim. A recent announcement of Cadence innovative new mixed-signal fast spice Spectre-FX allows designers to fill in this solution gap. In this presentation, we would like to share the early adoption experience and result in terms of tool use model, performance and accuracy result.

Moving forward to advanced process, digital block in custom design faces many challenges. E.g., complicate design rule for DRC, time-to-market pressure. This talk demonstrate the collaboration of TSMC and Cadence for innovative custom digital implementation flow in custom design. Custom digital block could be PnR by Innovus and still keep schematic based design in Virtuoso. By leveraging the power of APR tool, custom digital block could be completed in short turnaround time and final result could be stored back to OA database and still keep schematic connectivity as well to enable further verification flow in Virtuoso. No additional effort for customer to customized TSMC design collateral since all related TSMC design collateral are ready for this innovative design flow by the collaboration of TSMC and Cadence.

In the presentation, we will introduce the latest advances in the integrated MATLAB® and Virtuoso® ADE workflow for data visualization, analysis, characterization, and verification of advanced AMS designs. You’ll also learn about behavioral modeling and simulation of mixed-signal systems in Simulink® and co-simulation and export of DPI-C System Verilog models for final simulation in Virtuoso.

Latest innovations from the Digital Design and Implementation group relating to power savings, advanced node coverage , machine learning and multi-chipset flows will be presented.

In traditional flow, the feed-through paths are implemented by the physical designers, so that not be considered at synthesis stage. Designers have no chance to realize the real impacts caused by feed-through paths before moving to P&R stage. This mismatch between the synthesis and physical design leads to un-expected impacts in timing, congestion and utilization rate, especially for top-level design. Top-level physical designers may relieve utilization to alleviate the side effects from the feed-through paths. To cope with this problem, it costs additional iterations from synthesis to floorplan refinement, and even through sizing up entire core area in the worst case. In practice, iterating for considering the feed-through paths consumes weeks to handle the issues. In this work, we propose a novel solution based on Genus iSpatial to represent feed-through impacts during top-level synthesis. According on the results with feed-through, designers can refine logic and physical designs at early stage to avoid un-necessary iterations. The new solution can perform better efficiency in design and feed-through planning compared to traditional solution.

MediaTek is the largest fabless IC design house and have different product lines. As chip becomes larger and complex, there is a growing number of patterns request to do power integrity analysis. It is not possible to analysis IR result for hundreds of patterns within the requirement of tape-out schedule. In this section, to achieve both schedule and quality of design, we show a smart scenario selection flow with Cadence Voltus vector profiler. 

Vector profiler is a new technology for pattern analysis. Vector profiler ranks the high power window in patterns based on user defined criteria, such as current, delta power, instance coverage and so on. According to ranking result, it extracts first few windows for vector based simulation and extracts toggle rate of those windows for vectorless simulation.

The new methodology result shows a reasonable run time for hundreds of patterns. It also achieves over 90% instance toggle coverage. By using this flow, We are able to analysis more patterns and achieve a higher quality design within tape-out schedule.

Innovus Mixed Placer is a powerful new generation engine which can handle macros and STD cells' placement concurrently. It provides PPA (power, performance, area) improvements. In addition, it can reduce the turnaround time to find an optimal floorplan in comparison to conventional manual floorplan method. In this presentation, we will introduce the attractions of Mixed Placer via our case and tapeout experiences. We will also talk about the area for improvements which are still under development with Cadence.

As consumers expect richer, more interactive, and more intuitive user interfaces, the way compute systems are engineered must continually evolve to keep up. Ever increasing compute performance is one of the key principles of the Arm Total Compute strategy. Arm and Cadence have been collaborating for many years on delivering implementation flows for the various IP components of Total Compute. During this session both Arm and Cadence will demonstrate how the Cadence Digital full flow is being used to deliver the power and performance goals required for Total Compute, and how system on chip designs can benefit from this shared experience.

The Future of Timing Constraint Validation - A New and Smart Solution in Renesas to Create Precise SDC Using Conformal Litmus

The validation of timing constraints (SDC) had become a time consuming manual and inefficient process due to increasing design complexity in LSI designs with inaccurate SDC verification tools. The major problem was that these tools reported numerous insignificant occurrences as error. To solve the problem, we have been partnering with Cadence on a new solution, Conformal Litmus, which addresses Renesas’ vision of timing verification. We have applied Conformal Litmus to several projects and have been able to identify the root cause of errors and reduce verification resources by 50%. In this presentation, we will introduce how we improved our design efficiency with the developed features in Conformal Litmus.

Get the latest 21.1 software release updates for Tempus Timing Solution and Voltus Power Integrity Solution. Learn key functionalities that allow our customers to shorten their time-to-market while achieving the best PPA.

Next-generation TWS earbuds and Bluetooth headsets demand higher sound quality, rich interactivity, and environmental awareness. They need to concurrently run the latest Bluetooth audio codecs and mitigate the effects of noise. Extending battery life while meeting these needs is a challenge. This presentation introduces an ultra-low energy DSP that is optimized for multi-modal interaction and contextually aware processing of sound, including speech, voice, and music for wearable and hearable devices and always-on applications for a wide range of consumer devices.

Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

This work represents the design and TIE implementation of a flexible yet fast 2n-point complex FFT architecture using FIFO. Four parallel read-write queues are used instead of shared data memory to improve the overall performance and throughput. The proposed FFT architecture follows the basic concepts from Radix-2 and Stockham-FFT algorithms, but stands unique with the data flow patterns. This approach requires only 768 cycles to perform complex 4K-FFT when compared to the 2070 cycles requirements in the ConnX B20 (library) itself. It is achieved by a total of 2048-bits read and write per cycle (2 to 4 queues in parallel).

The twiddle factors for the FFT can either be computed during runtime or pre-computed and stored in a separate reusable queue. The latter technique is followed in this work in order to reduce the computational complexity. Four hardware parallelization methods are proposed to achieve better performance based on the FFT sizes. In every cycle, each method reads data-points from two different queues, performs butterfly operation and writes the results not necessarily in the same two queues. The 1st method takes only 2-data points per cycle and performs the butterfly operation, whereas the 2nd, 3rd and 4th methods take 16-, 32- and 64-data points per cycle respectively. Each data point is considered as 16-bits real and 16-bits imaginary fixed-point complex element. The 4th method requires two 32-data points from two respective queues, which corresponds to the data width of 1024-bits per queue.

In each cycle, the 1st method reuses 4 32-bit multipliers and 8 16-bit adders that are required to perform a butterfly operation and the 4th method requires reusable 128 multipliers and 256 adders. The data flow pattern followed in this work ensures the reusability of twiddle factors. Thus the twiddle factor computation or the twiddle queue read is not required in every cycle. With any fixed hardware parallelization methods, the FFT size can be configured. For instance, with the 1st method, 24 to 212-point FFTs or above can be realized. Similarly, with the 4th method, 29 to 212-point FFTs or above can be realized. With the 1st method, a 16-point complex FFT takes 32 cycles to perform the whole operation. The 4th method computes 512-, 1024-, 2048- and 4096-FFTs within 72, 160, 352 and 768 cycles respectively. The application specific SIMD and FLIX instructions are created using Tensilica Xtensa and the FFT architecture is realized using ConnX B20 DSP.

Cadence and NVIDIA partnership to utilize GPU in Allegro PCB design and Allegro Package Designer Plus, gain performance over traditional OpenGL. Significantly improve the performance and quality of display.

In the digital age, digital data is the key to moving businesses forward into growth. The applications of digital data across a wide range of sectors not only change our day-to-day lives, but also offer huge opportunities for companies to create competitive advantages through mining potential information and delivering effective strategies. 

Over the past decade or so, Google has become one of the most valuable data centers in the world. Google Maps, its famous application of digital data, successfully changed human behavior and enhanced the value of data. Despite the widespread use of digital data nowadays, the electronics industry still holds back its development due to a lack of sufficient and complete component digital data for product design and manufacturing. 

In order to resolve this issue, Footprintku is dedicated to developing a series of innovative digitization technologies. Footprintku utilizes its unique AI and automation technology to digitize PDF files of data for establishing an integrated data hub, which satisfies different users’ requirements. With the development of this electronics data hub, the industry will effectively evolve in the near future.

Many PCB Design teams face a moment of truth when they hand over their design files to the reveredsignal and power integrity engineers. Despite following the physical constraints, you know the SI/PI team is going to throw it back over the wall with a list of things that must be corrected. What if there was a better way? What if the PCB Design tool contained in-design analysis? What if you could eliminate 10 percent of those ECOs? What about 50 percent … maybe even 75 percent? Your PCB would be off to production weeks earlier. Cadence now has in-design analysis for signal and power integrity that does not require any models. On the other hand, if you choose to store your IBIS models with the design, you can perform more advanced SI analysis while designing.

Engineers and designers today need many different tools for their CFD analyses. Omnis combines them all into one single environment, from meshing to solving to optimization. High-performing technology in a slick, easy-to-use interface, streamlines the workflow of all its users. From the detailed analysis of a single component (e.g. IC chip) all the way to simulating a full system (e.g. entire car), with Omnis users can combine the different physics, scale fidelity to need and create as many designs as desired. It can be fully automated, driven by AI models and optimization algorithms, and is open to third-party software through powerful APIs.

Cadence®AWR Design Environment®Version 16 (V16) introduces groundbreaking cross-platform interoperability to support RF IP integration for heterogeneous technology development across Cadence Allegro®PCB Designer, Virtuoso®System Design, and Virtuoso RF Solution platforms,delivering up to a 50% reduction in turnaround time compared to competing workflows.The V16 release also provides seamless integration with Cadence’s Clarity™ 3D Solver and Celsius™ Thermal Solver, delivering unconstrained capacity for electrothermal performance analysis of large-scale and complex RF systems.

The design effort for upcoming integrated circuit and package technologies is rising because of increasing complexity in production. To cope with that situation it is essential to reuse pre-qualified elements for handle complexity. For package technologies this becomes more and more apparent. Looking at the requirements for 5G applications in a radio frequency up to 60 GHz for package technologies it is no longer feasible to start from scratch. So it becomes more and more import to use prequalified elements for a technology. This paper deals with the implementation of RF-structures for manufacturing and characterization and the how to cover the interaction in the system across IC and different package levels with dedicated tooling. For upcoming package technologies it is getting more and more important to include these devices into so called Assembly Design Kits (ADK) to enable designs by potential customers.

In this paper a package that includes two different levels of integration is presented. Package level one is a rdl technology for flip-chip assembly and level two is based on eWLB and is integrated on level one as a package-on-package approach. Both are wafer level package technologies. The paper deals with that technology but the general approach is valid for other package technologies as well.

The flow starts with designing within Cadence Virtuoso with multiple modification in terms of addressed frequency and optimization according RF properties like gain, loss or target impedance. The designs are transferred into radio-frequency analysis tools like EMX or Clarity to investigate their behavior on a model basis. This enable the possibility to optimizes the elements according to certain target parameters across technologies.

After finishing the design process, these elements are produced on a 300 mm wafer. After production the wafers are ready for characterization. Due to the distribution across a wafer and running lots with multiple wafers, characterization will also include statistics within wafers and across wafers and the reproducibility of the structures can be assured. All the results are bundled into a construction kit with a Cadence-based ADK involving symbol, schematics and layout for future designs and also models for running analysis based on these elements. A set of elements are available for the listed package and IC technology for usage and transfer to customers.

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

Next generation of AI/HPC/Networking chips brings challenge of hyper scale, ultra-speed interfaces, advanced package methodology allow to address CoWoS and InFO are the most power and area efficient platforms for multi-die integration. Considering the density and performance limitations of 2.5D advanced packaging, to stacking dies using copper-to-copper hybrid bonding at the chip level, enabling new types of packaging from 2.5D to 3D. Overcome SI/PI simulation challenges of 2.5D to 3D technology with Cadence Clarity for D2D and HBM2E/HBM3 are very effective solutions

Nowadays, HBM is widely applied on big-data calculation, networking applications, and high-speed graphic processing, etc. Nevertheless, parallel data transporting is a more efficient way for die-to-die communicate. In this presentation, to pursue a higher bandwidth channel between two SOC, we design the 16Gbps parallel bus on two general interposers and come out with a performance comparison of two different interposer types.

Power integrity on PCB and Package are closely related to chip level design. Die current is critical to plan PCB and Package components and construction.

Therefore, Die-aware target impedance is useful to design and decide PDN structure at early design stage.

As a supplier of GDDR6 design IP for memory controllers, Cadence has a holistic solution of design and analysis tools that implement and simulate the IP in the chip as well as interconnect in the IC package and PCB. The high-performing GDDR6 memory interface is essential to graphics cards, game consoles, high-performance computing (HPC), and machine learning applications. However, it can be quite daunting for a signal integrity engineer to validate a design that will perform at maximum speed. Come explore the successful process where Cadence customers use Clarity and Sigrity X technologies to ensure GDDR6 is implemented to enable maximum performance and minimum cost.

To achieve the quality tape out automobile SoC and meet the requirement of ISO-26262, it requires sign off whole chip with DFT scheme. Such DFT scheme needs to deploy Logic BIST and Memory BIST operation during power up and mission mode is a new challenge for verification. This causes long iteration on “Regression and Debug” turnaround time which dominates tape out schedule and most of debug happen on Gate-level simulation. GUC DV team proposes a flow to involve and setup Palladium Z1’s Testbench Acceleration platform in the early stage of project execution. GUC applied this flow on real project and this flow and platform contribute to silicon back with 1st cut work.

In the past experience, it is found that many problems mostly occur due to interaction of multiple functions. However, there is no strategy for verifying multiple functions together in the past. Most of the combinations are verified only when someone thoughts of, but most of the problems arises from a possibility that has never been discovered. Therefore, this paper tries to propose a systematic architecture to automatically generate various cross-functional test scenarios to achieve the purpose of cross-functional verification.

Perspec can be a solution. We define a structure model in Perspec. Base on the shell, we can automatically generate mix scenarios of various functions. Not only reduce the complexity of human writing, but also achieve the possibility of reuse test scenarios. While generating testcaes, coverage is also generated. We can figure out the holes that may be overlooked in the coverage data, and it is more able to quantify the test intensity between different functions.

We are already successful to enable CPU subsystem verification via perspec. However, there are user commands in ASIC without the general ISA. Nowadays, some chips are combined with various hardware and software acceleration schemes, which have achieved great success in ASIC. However, due to the diversity of rapid requirements, it is very difficult to have a well-defined methodology that can be well applied to all kinds of customization in a timely fashion.

Therefore, a pretty novel approach with systematic and flexible architecture is proposed to automatically generate complicated data flows’ paths exhaustively and propagate heavy dependency constraints across these legit paths.

Perspec can fully fit this approach. We define a general framework model that is very easy to be extended based on new features and portable across different projects and teams quickly. It not only increase the productivity and quality of test patterns in ASIC but also achieve the possibility of data flow paths that are not considered originally.

This presentation demonstrates a successful formal story to sign-off the nested vector interrupt controller (NVIC) design by 

applying the architecture specification in Arm ARM (Architecture Reference Manual) as the golden behavioral checkers.

The previous similar work only achieved ~20 cycles bounded proven in partial configuration due to the tool capacity issue.

This time, with the following strategies, we successfully push it to fully proven, fully configured for the design sign-off standard.

                Strategy 1: Raise the assertion checkers to the higher level: from micro-architecture dependent to architecture level. 

                Strategy 2: Re-phrase the assertions and make it tool friendly. (Prove an assertion by contraposition law: !Q→!P, instead of P→Q)

                Strategy 3: Well-known formal abstraction techniques: non-deterministic oracle and reset value abstraction.

Post netlist simulation consumes lots of time.

Simulation with dumping waveform takes even more of time.

We require a flow that can rewind to previous timing and turn on waveform dumping if needed to help us debug.

Restart flow is exactly what we need.

It’s of high importance to do simulation in scenario close enough real-chip application in verification, especially developing some high-speed module such as IPU, DSP. However, the traditional methods such as simulation in rtl-level by third-party tools (nc, vcs …) would take a long time to dump enough information. At the same time, the sim case may be way too humble compared with real-scenario application. Platform like FPGA can hold more complex and longer verification, but sometimes it’s difficult to achieve the same condition as reality because of low clock frequency, or lack of enough proportional clock source, even sometimes overload of utilization when faces huge design.

Palladium Z1 emulator offers powerful tools and enough resource to make it possible to run real-scenario firmware. And through place clock proportionally, developer can decide performance of module, knowing whether it’s work in line with expectations in real-chip.

This presentation will focus on how to make a database which keeps conditions close enough to real scenario when handing high-speed module.