IBM and Cadence

IBM is a technology firm headquartered in Armonk, New York. The company manufactures and sells hardware and software, and it offers infrastructure, hosting, and consulting services ranging from mainframe computers to nanotechnology.

In 2011, Fortune ranked IBM the 18th largest firm in the U.S., as well as the 7th most profitable. Forbes ranked the company 31st largest firm globally for 2011. Other 2011 rankings include No. 1 company for leaders (Fortune), No. 2 best global brand (Interbrand), No. 3 green company (Newsweek), #12 most admired company (Fortune), and #18 most innovative company (Fast Company). IBM employs more than 425,000 employees in more than 200 countries.

Designing circuits with sub-micron technologies presents a unique challenge to meet more stringent specifications despite increasing statistical variation and complexity. To achieve firstpass success, it’s necessary to use advanced SPICE models and achieve high correlations between actual silicon and circuit verification. This requires a high degree of cooperation and integration between modeling engineers and circuit-simulation providers.

Last year an IBM modeling team initiated a verification effort with Cadence using silicon on insulator (SOI) advanced process nodes as a pilot. The goal was to generate a robust, exhaustive, and efficient model qualification flow using Cadence Virtuoso Spectre Circuit Simulator for IBM SOI process nodes. The SPICE verification flow was implemented in Cadence Virtuoso Multi-Mode Simulation 10.1 and above.

The model qualification process is critical because the IBM team must work on tight schedules to meet customer needs. In addition, each compact model must also undergo a stringent qualification process by the Compact Model Council (CMC) before it’s released to customers.

“Cadence Virtuoso unified custom/analog flow, including a comprehensive regression test suite and advanced simulation technology tests, reduced our overall SOI model validation cycle time,” says Carl Wermer, advisory engineer, IBM.

The new qualification process has also improved the IBM team’s productivity and SOI process node accuracy. Customers don’t have to wait as long for the latest model release, and they can easily work with the model because the simulators properly support it.

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The Cadence team is insightful, quick to help when we need guidance using Cadence technologies, and quick to recognize and respond when there are problems.

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Several IBM senior device modelers are part of the CMC, which supports industry review, testing, and adoption of new compact model codes. IBM and Cadence are both part of the CMC, and began working together as part of this organization.

The IBM modeling team started using Cadence technologies to verify compact models in 1998. The companies’ SOI work relationship started in 2000 when IBM customers who had been using Virtuoso Spectre Circuit Simulator with bulk models moved to SOI and wanted to continue to work with Cadence simulators.

IBM begins field-effect transistor (FET) device modeling qualification each time a new SPICE compact model for SOI, such as Berkeley Short-channel IGFET Model SOI (BSIMSOI), is released. The modeling team uses internal and vendor tools to build a model and test it against many conditions to confirm the fit is correct and consistent.

“After the CMC accepts a new or updated compact model, we implement it in the IBM internal simulator and fit the model to proprietary device data or targets,” Wermer explains. “From there, we still need to support customers inside and outside of IBM who use Spectre for their design work. It all has to become part of the Cadence common model interface and be supported by Virtuoso Multi-Mode Simulation.”

IBM has internal and external customers who primarily use Virtuoso Spectre Circuit Simulator, but sometimes use other commercial simulators. So when a model is generated the IBM modeling team needs to check that the model implementation and results are consistent across many vendor simulators.

In addition, IBM has implemented many features within the compact models to support parameter variability (process statistics) and allow designers and developers to predict process sensitivity. As process dimensions shrink and more complex solutions are required, these features need frequent updates and changes.

“We run Virtuoso Spectre Circuit Simulator to compare graphical outputs and check basic functionality,” Wermer says. “Then we take advantage of Spectremdl scripts for more complex simulations and measurement capability. Virtuoso Spectre Circuit Simulator has proven extremely efficient in parsing all the model code we use and giving good run times, particularly for large Monte Carlo simulations.”

The IBM modeling team also compares a large set of outputs to ensure consistent implementation of its models across Virtuoso Spectre Circuit Simulator and other commercial simulators using Perl scripts and an internal IBM tool.

As IBM customers make the transition from bulk to SOI, there’s often confusion about what to do with floating body nodes, concern about slower run times, and other convergence challenges.

“Many design teams have cleared these early hurdles and are designing successfully in SOI,” Wermer says. “For convergence questions, we first look for problems with the compact models and the customer set-up, and then we rely on the Cadence Customer Support team to take over.”

For example, during the BSIMSOI project a customer asked the modeling team for a bug fix of the compact model. The update wasn’t scheduled for several months, and the fix included challenging code updates.

“Cadence proposed an elegant solution,” Wermer says. “The model cards now support an additional parameter so we can include or exclude bug fixes in the code from Berkeley. If a value wasn’t assigned it defaults to the original code to avoid unexpected results and preserve back compatibility.”

When testing flagged an unexpected change in the BSIMSOI code, the Cadence Customer Support team quickly scheduled meetings to work with IBM and make sure the regression testing was updated to reflect the modeling team’s needs. Both parties identified an exhaustive set of regression tests to be used by both Cadence and IBM.

“Cadence initiated the effort to align its regression tests and verification procedures to match with ours, and worked closely with us to close the gap,” Wermer explains.

The companies identified an IBM SOI process node technology file that could be used by Cadence R&D to ensure all parameters extracted by IBM are tested. They identified how often those regression tests should be performed and how they would be communicated to IBM.

“One key issue was to make sure our large suite of model output measures for device current and charge, along with derivatives like the related capacitance and outputs like gm/gds, would be fully tested by Cadence,” Wermer says. “Cadence added more regression tests to fully match with our model validation.”

Together, IBM and Cadence initiated a verification effort for SOI advanced process nodes. The end results was a robust, exhaustive, and efficient model qualification flow that provided the IBM modeling team the solution it needed to meet stringent customer requirements and timelines. The qualification flow has reduced IBM’s validation cycle time and improved productivity and process node accuracy.

“The Cadence team is insightful, quick to help when we need guidance using Cadence technologies, and quick to recognize and respond when there are problems,” Wermer says. “We look forward to continuing our work with Cadence.”