Denali Controller IP for GDDR6

Artificial intelligence (AI), high-performance computing (HPC), cryptocurrency mining, and graphics applications generate and consume large volumes of data and video and require very high memory bandwidth. The Cadence Denali DDR IP is a family of high-speed on-chip interfaces to external memories, with the bandwidth necessary to support these applications.

The latest, the Cadence Denali Controller IP for GDDR6, provides low latency and very high bandwidth, while supporting extensive value-added features including, but not limited to reliability features.

Developed by experienced teams with industry-leading domain expertise and based upon Cadence’s widely proven DDR controller IP, the Controller IP for GDDR6 can provide customers with ease of integration and fast time-to-market.

The Controller IP is engineered to quickly and easily integrate into any system-on-chip (SoC), and is verified with the Cadence Denali PHY IP for GDDR6 as part of a complete memory subsystem solution that also includes Cadence Verification IP (VIP). The Controller IP is designed to connect seamlessly and work with Cadence or thirdparty DFI-compliant PHY IP. Developed for and available in alignment with the PHY IP on advanced semiconductor process nodes, the Controller IP is designed to be robust under various traffic loads and to have interoperability with various supplier memory chips. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of Denali memory interface, analog, and systems and peripherals IP.

The Controller IP is designed to provide the flexibility needed to enable application-specific configurations ranging from high-performance networking and mobile to consumer. The host-side port interface can be configured to support multiple ports, each of varying width and with different AMBA protocol and clocking options. The command queue intelligently schedules traffic from the port arbiter to maximize data throughput efficiency. The Controller IP includes various feature options such as low-power modes required by mobile applications and several reliability features required by enterprise applications.

The Controller IP was engineered to be highly configurable, allowing the selection of application-specific features, which in turn yield an area-optimized solution per application. The controller is also developed to provide maximum throughput across many different traffic profiles. 

The Controller IP uses multi-stage reordering algorithms architected for use with traffic profiles from many different applications. Performance-tuning parameters allow performance optimization based on individual system and memory requirements.

The Controller IP supports one 2x16-bit GDDR6 device (coplanar) or two 2x16-bit devices in clamshell configuration. Multiple channels may be instantiated for capacity or bandwidth expansion. 

The Controller IP also delivers a wide array of capabilities to address emerging DDR DRAM subsystem reliability, availability, and serviceability (RAS) requirements. Some of these capabilities include embedded support for ECC and other vital error detection and error prevention capabilities such as parity protection and DRAM data scrubbing. All the Controller IP configurations support power-down and self-refresh. 

Natively supports any mix of Denali and AXI interfaces. Priority-per-command on AMBA 3 AXI interfaces and QoS on AMBA 4 AXI interfaces improves latency and controller QoS, especially for transactions delivered through an inter-connect fabric. Flexible synchronization allows low-latency synchronous port connection, reduced-latency pseudo-synchronous ratio port connection, or highly flexible asynchronous port connection. 

The DFI 5.0-like PHY interface connects to Cadence or third-party PHYs. An 8:1 frequency ratio is used between the DRAM and the memory controller to assist timing closure. 

The Controller IP is available with various configurations and supports the following protocol:

For more information, visit Design IP.