IC/Package Co-Design and EM Co-Simulation with Virtuoso RF Solution and Clarity 3D Solver

The impact of package design on IC performance is getting more and more important, especially for high-performance and high-speed ICs. For example, the coupling interference between die and package and the impact of package to on-chip passive components and critical signals are getting more and more obvious. Traditionally, ICs and packages are designed on different planforms. Nowadays, the disjointed tools are no longer sufficient to address the level of complexities and time-to-market constraints. For chip-centric IC design, we need a system design solution to help build the bridge between IC design and package design, to consider them as a whole during the design period and to realize the electromagnetic (EM) analysis with both IC part and PKG part included, which helps make simulation result as close to real measurement as possible, so that we can improve product success rate and decrease product time-to-market. Using two major flows in the Virtuoso RF Solution, implementation flow with IC/PKG co-design in Virtuoso and an EM analysis flow in Virtuoso with Clarity as EM solver. With the implementation flow, we can import package physical design into the Virtuoso platform easily for IC/package co-design. It helps decrease manual errors due to misunderstandings and improve design efficiency. With the EM analysis flow we realize high-performance and high-capacity EM simulation for both the IC-only case and the IC+PKG case. The Clarity 3D Solver can tackle the most complex EM challenges with gold-standard accuracy, virtually unlimited capacity and excellent simulation performance. With the EM assistant in Virtuoso Layout EXL, we can export all needed IC information into the Clarity GUI easily, we can combine IC part and PKG part in Clarity conveniently, and do EM co-simulation, thus get the coupling interference between IC and PKG with good accuracy. With S-parameter models generated with the Clarity Solver, we can realize system-aware simulation and get a good estimation on critical specs before tapeout.