DDR Crosstalk Problems Where You Least Expect Them

The lighting fast speeds of double-data-rate 5 (DDR5) data, require many signal integrity (SI) engineers to invest significant analysis time, ensuring that data signals will meet the bit-error rate (BER) and mask requirements associated with the Joint Electron Device Engineering Council (JEDEC) data bus specification. This talk from Jayaprakash Balachandran, technical lead at Cisco, shows that while the data bus gets all the glory, there are other parts of DDR design and analysis that also deserve attention. See how Cisco engineers spent part of their DDR analysis time and uncovered a problem before the prototype stage, thereby avoiding a costly re-spin of a PCB.