HCHTvfuZtZCauVbjXDfBsZ
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Saving Routing Resources, Speeding Up Timing Closure at Freescale Semiconductor
Routing and timing closure were big challenges on the high-performance cores developed by Freescale Semiconductor. How did the engineers improve these processes? Watch this video to hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence® Encounter® digital implementation tools to save routing resources and speed up the timing closure process. Learn more about Encounter tools here: http://bit.ly/1xTng38
Last Modified: August 22, 2015
Duration: 4 min