MRDi2mB4DFsgCLoeStdx6j
How New DFT Solution Trims Test Time for Digital Logic
Hear Paul Cunningham, VP of R&D at Cadence, explain how the company's new Modus™ Test Solution reduces test time for digital logic by up to 3X compared to other available solutions—without impacting chip size or yield.
Last Modified: March 23, 2016