Whiteboard Wednesdays: Inductance Extraction for Digital Designs

In this week’s Whiteboard Wednesdays, Cadence expert Varun Raj Garapati explains how designers can address inductance effects on clocks, especially on digital SoCs. Using Quantus Extraction Solution for FinFET designs, designers can overcome reliability issues stemming from Inductance effects. To learn more visit https://www.cadence.com/go/quantus-extraction