HJNEi8gJ7deoDuDu27Xf3t
![](https://play.vidyard.com/HJNEi8gJ7deoDuDu27Xf3t.jpg)
STMicroelectronics: Improving Productivity with Virtuoso SPD
In this Expert Insights video, Vikas Chelani, Sr. Layout Designer of ST India, describes the challenge of making IP memories compact and efficient despite increased routing and logic complexities. Using Cadence® Virtuoso® Symbolic Placement of Devices (SPD) reduced both his preliminary area estimation and device placement cycles, leading to a 35% productivity gain.
Last Modified: October 24, 2016