Transistor-Level Reliability Analysis for Advanced Node

Sangtae Bae, an analog/mixed-signal circuit designer at IBM, designs high-speed interfaces for IBM's server chips.
Bae and his team needed a method to verify circuits will operate in silicon, reliably well over expected life of products.
In this 4-minute video, Bae explains how reliability simulation in Cadence® Spectre® Accelerated Parallel Simulator (APS)
ran from Cadence Virtuoso® Analog Design Environment (ADE) helped IBM perform reliability analysis efficiently
and get to market faster with its server chips.