Cadence PCIe 5.0 Sub-system Silicon Demo

Cadence demonstrates the IP industry’s first full 8-lane PCIe 5.0 sub-system solution on a single chip. The subsystem consists of Cadence’s latest PCIe 5.0 PHY and controller technology interoperating at 32GT/s with leading OEM server platform and test equipment vendors. The subsystem solution is available in 7,6,5, and 3nm process nodes with scalability to support up to 16-lane configurations.