EdMxWvhiaZV8GF3K5vBiPz
![](https://play.vidyard.com/EdMxWvhiaZV8GF3K5vBiPz.jpg)
A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and Process Targets
A DAC 2017 Qualcomm presentation on High Level Syntesis Design Flow for Scaling to Multiple IP, SoC, Process Targets. Motivation and needs to be distributed, scalable , Hierarchical HW System
Last Modified: June 19, 2017