Overview
Gold standard for JEDEC® HBM3 memory device for your IP, SoC, and system-level design verification.
First to market with multiple early adopters of production designs.
This Cadence® Verification IP (VIP) provides support for the High-Bandwidth Memory (HBM3) interface. It provides a highly capable compliance verification solution applicable to IP, system-on-chip (SoC), and system-level verification. The Cadence Memory Model for HBM3 models a single channel of HBM3 DRAM; this model can be replicated for multiple channels and stacks. The Memory Model for HBM3 runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
Speed (MHz) |
|
Mode Registers |
|
Addressing |
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HBM3 Functionality |
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