Joules Power Calculator Training
日付 | バージョン | 国 | 場所 | |
---|---|---|---|---|
Scheduled upon demandOn demand | お問い合せINQUIRE |
バージョン | 地域 | |
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21.1 | Online | ENROLL |
20.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 Hours)
Become Cadence Certified
Course Description
This is an Engineer Explorer course for designers familiar with low power concepts and its analysis.
The Cadence® Joules™ RTL Power Solution is an RTL power analysis product that provides a unified engine to compute gate Netlist power and estimate power for RTL (within 15% of signoff power). In this course, you will learn Joules' RTL power flow. You will also learn how Joules integrates seamlessly with the Cadence Palladium® emulator and Genus™, various strategies to debug low stimulus annotation, and how you can better correlate RTL power with signoff. You also learn various ways to report and analyze the power of the design.
Learning Objectives
After completing this course, you will be able to:
- Identify solutions and features for RTL Power using Cadence Joules RTL Power Solution
- Set up and run RTL Power Flow with Joules
- Explore the Graphical User Interface (GUI) capabilities of Joules
- Estimate power using vectorless power, stimulus flow, RTLStim2Gate flow and replay flow
- Interface Joules with Palladium
- Estimate power at the chip level
- Navigate the design and data mining using Joules
- Analyze ideal power
- Analyze ODC-driven sequential clock gating
- Identify clock gate low activity registers
- Analyze power and generate various power reports
- Analyze results through GUI
- Explore RTL shell for customization
- Debug power issues in Joules
- Identify Genus-Joules integration
Software Used in This Course
Joules RTL Power Solution
Software Release(s)
JLS211
Modules in this Course
- Introduction to Cadence Joules RTL Power Solution
- Fundamentals of Joules
- Estimating the Power
- Joules Power Exploration Features
- Analyzing the Power
- Debugging Issues in Joules
- Genus-Joules Integration
Audience
- Design engineers doing RTL power analysis and calculation
Prerequisites
You must have experience with or knowledge of the following:
- VLSI or Genus Synthesis Flow
- Low-power concepts
Or you must have completed the following course:
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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