Layout Verification
Delivering a faster path to final signoff
At advanced nodes, you’ll have more mandatory design for manufacturing (DFM) checks to address lithography, etch, and mask systematic manufacturing variations that can cause parametric yield loss. Cadence’s layout verification tools in the Virtuoso® custom design platform support in-design manufacturing signoff. The tools also help you mitigate layout-dependent effects (LDE) during layout creation via technology that provides in-design LDE analysis and optimization.
We also provide, via the Cadence® Physical Verification System, in-design and back-end physical verification, constraint validation, and reliability checking capabilities that can accelerate final signoff.