Conformal Equivalence Check & Conformal ECO Training
날짜 | 버전 | 국가 | 위치 | |
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Scheduled upon demandOn demand | EnrollINQUIRE |
Length: 3 Days
Conformal Equivalence Checking
Course Description
In this course, you learn to use the Conformal® Equivalence Checker to perform functional verification. You learn the basic flow of equivalence checking and how to run hierarchical comparison of designs. The lab exercises follow major topics and are designed to be directly applicable in design and design verification. Upon completion of this course, you will be able to set up and verify your designs, analyze the results, and debug failing results.
Learning Objectives
After completing this course, you will be able to:
- Use Conformal logic equivalence checking for flat and hierarchical design comparison
- Read libraries and designs
- Apply design constraints and modeling directives
- Apply the mapping process and debug unmapped key points
- Apply the compare process and debug non-equivalent points
Software Used in This Course
- Conformal XL
Software Release(s)
CONFRML221
Modules in this Course
- Overview of the Conformal Product Family
- Introduction to Logic Equivalence Checking
- LEC Flow: Setup Mode
- LEC Flow: LEC Mode
- Hierarchical Comparison of Designs
Audience
- ASIC Designers
- Logic Designers
- Verification Engineers
Prerequisites
You must have experience with or knowledge of the following:
- HDL
- Logic Design
Conformal ECO
Course Description
The Conformal® ECO Designer combines logic equivalence checking (for the most complex SoC and datapath-intensive designs) with functional ECO analysis and generation, design netlist modification, clock domain synchronization, and semantics checks. With a complete ECO solution that spans different parts of the RTL-to-GDSII flow, design teams benefit from automation, predictability, and the highest-quality ECOs. This course provides an in-depth look at the software along with hands-on experience required to use the tool.
Learning Objectives
After completing this course, you will be able to:
- Explore the many options and capabilities of Conformal ECO
- Use Conformal Engineering Change Order (ECO) for flat and hierarchical designs
- Generate a functional ECO patch, apply it to a design, optimize it, and map it to a specified technology
- Run a hierarchical design through ECO and run a comparison to prove the ECO is equivalent
- Run a postmask ECO using Conformal ECO GXL
Software Used in This Course
- Conformal XL
- Conformal ECO Designer XL
- Conformal ECO Designer GXL
Software Release(s)
CONFRML211 GENUS211
Modules in this Course
- Introduction to Conformal ECO
- Flows Overview
- Basic ECO Commands
- Flattened ECO Flow
- Hierarchical ECO
- Postmask ECO
- Debugging and Best Practices
- Spare Gate Strategies
- ECO Cut Point Flow
Audience
- Logic Designers
- Place and Route Designers
- Verification Engineers
Prerequisites
You must have experience with or knowledge of the following:
Conformal LEC
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus