DE-HDL Library Development using DE-HDL Training
날짜 | 버전 | 국가 | 위치 | |
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Scheduled upon demandOn demand | EnrollINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
In this course, you learn to create schematic libraries for Allegro® Design Entry HDL and footprint libraries for use with the Allegro PCB Editor. About 75% of the course time is focused on front-end schematic library development, and the remaining 25% is spent on back-end footprint creation. You create a project area for building schematic symbols, pin maps, part tables, and package symbols. You also test these part definitions in a front-to-back flow.
Allegro PCB Editor footprint creation is also covered in the Allegro PCB Editor course. See the list of Related Courses below.
Learning Objectives
After completing this course, you will be able to:
- Set up for library development
- Create symbol, package, part table, and simulation views
- Create asymmetrical and split parts, and build new parts from existing ones
- Test parts
- Build padstacks and package symbols
Software Used in This Course
- Allegro PCB Librarian
Software Release(s)
SPB22.1
Modules in this Course
DE HDL Library Development
- Introducing PCB Librarian
- Setting Up a Build Area
- The Symbol View
- The Chips View
- The Part Table View
- The Simulation View
- Testing the Part
- Building a 74LCX125
- Building a Resistor Network
- More Part Building
- Advanced Skills
PCB Editor Library Development
- Padstack Editor
- Symbol Editor
- Package Symbol Wizard
- Custom Padstacks
- Mechanical Symbols
- Edge Connectors
- Debugging Problems
Audience
- Library Developers
Prerequisites
There are no prerequisties for this course
Related Courses
- Allegro Design Entry HDL Basics
- Allegro Design Entry HDL Front-to-Back Flow
- Allegro PCB Editor Basic Techniques
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus