IC Package Design Flows
With complex advanced packages, you are faced with power integrity (PI), thermal, and signal integrity (SI) issues driven by increasing IC speeds and data transmission rates combined with decreases in power-supply voltages and denser, smaller geometries. Stacked die and packages, higher pin counts, and greater electrical performance constraints are making the physical design of semiconductor packages more complex.
Cadence IC packaging and multi-fabric co-design flows deliver the automation and accuracy necessary to expedite the design process. To address these issues, you need the latest releases of PI and power-aware Cadence Sigrity SI tools that can be used throughout the design process.
The Cadence Integrity System Planner unifies IC, interposer, package, and PCB data, so signal-to-bump/ball-assignment and connectivity/routing-pathway scenarios can be easily derived and evaluated. The system is unified in a single environment, enabling system-level design and analysis. This allows IC/package/PCB co-design and implementation to take place, as well as constraint-driven power delivery network (PDN) design with an integrated layout and analysis solution.