Use this education kit to teach the different technologies and methodologies for verification and to work on practical exercises verifying designs.
Course Aim
To explain to students the different technologies for verification and to give them practical exercises on how to verify designs.
Syllabus
1 |
Introduction to Digital Chip Design Development Flow |
2 |
Verification Types Through Development Flow |
3 |
Unit-Level/Subsystem/Full-Chip Verification Methodologies Cadence Verification Suite |
4 |
Introduction to SystemVerilog |
5 |
Introduction to UVM (2 parts) |
6 |
Introduction to Static Verification |
7 |
Introduction to Formal Verification + Introduction to SystemVerilog Assertions |
8 |
Introduction to Dynamic Verification |
9 |
Introduction to Emulation Overview of Cadence Palladium Overview of Cadence Protium |
10 |
Debugging Tools |
11 |
Introduction to Power Verification |