Use this education kit to teach how to use a shift-left methodology to develop hardware accelerations in compute-intense edge applications.

Kit specification

  • Summary: This set of six modules with lecture slides and lab exercises (in selected modules) is ready for use in a typical one-to-two-week seminar or a full-day workshop (full syllabus below).
  • Modular and Flexible Use: Educators can choose the modules to teach—use all the modules in the Education Kit or only those most appropriate to your teaching outcomes. All provided materials are editable and can be easily adapted for the educator’s needs.
  • Recordings: Videos can be used for self-study of the subject.
  • Level: Advanced. Students are required to have a solid understanding of computer architecture, hardware description languages, and C programming language.

All software tools required for the practical part are available through the Cadence University Program. In order to become a member of the Cadence University Program, please write to universityprogram@cadence.com for assistance. For the practical part on Tensilica processors, access to Cadence’s Tensilica University Program is required. In order to become a member of the Tensilica University Program, please fill out and submit application form or write to universityprogram@cadence.com for assistance.

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Course aim

To explain to students the principles of development of hardware accelerators using different approaches like extension of ASSP or high-level synthesis of a designated block.

Learning outcomes

Knowledge and understanding of

  • How to run an algorithm on the model of an ASSP, profile it, and understand the performance limits
  • How to create a processor extension, which addresses the performance limit, and verify the outcome
  • How to create machine learning accelerators in SystemC
  • How to model a virtual prototype on different abstraction levels
  • How to run high-level synthesis (HLS) and the difference between synthesizable and non-synthesizable SystemC
  • How to do architectural exploration using HLS
  • How to compare performance between different implementation approaches

Syllabus

No. Syllabus/th>
1 Overview and Introduction of Shift-Left Methodology
2 Xtensa Embedded Processors Tensilica and Toolchain
3 Debugging, Profiling, and Acceleration
4 High-Level Synthesis, DMA IP
5 Accelerator IP, Design, and Verification
6 Summary