Use this education kit to teach the fundamentals of digital implementation using the full Cadence digital flow.

Kit specification

  • Summary: This set of 18 modules with lecture slides and lab exercises (in select modules), is ready for use in a typical semester (full syllabus below).
  • Modular and Flexible Use: Educators have the freedom to choose which modules to teach – use all the modules in the Education Kit or only those that are most appropriate to your teaching outcomes. All provided materials are editable and can be easily adapted for educators’ needs.
  • Level: Beginner. Students are required to have a basic understanding of digital design, Verilog, and standard cells.

 

All software tools required for the practical part are available through the Cadence® University Program. To become a member of the Cadence University Program, please write to universityprogram@cadence.com for assistance.

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Course Aim

To explain to students the principles of the full digital implementation flow.

Learning outcomes

Knowledge and understanding of 

  • Complete Digital Implementation Flow from RTL to GDSII
  • How to run synthesis to generate a netlist
  • How to do optimal floorplan and placement
  • How to create routing and synthesize a clock-tree
  • What is timing optimization and power analysis?
  • How to fix timing violations
  • What is parasitic extraction and substrate noise analysis?
  • How to run gate-level simulation and logic equivalence checks
  • What is physical verification and chip finishing?
  • What is the outlook for the next generation of EDA tools for digital implementation flow?

Syllabus

   
1 Introduction to Digital Chip Design Development Flow
2 Introduction to Logic Design, Creating Digital Design, Simulation of Digital Design
3 Introduction to Synthesis
4 Introduction to Timing
5 Introduction to Floorplanning
6 Introduction to Power Planning
7 Introduction to Placement
8 Introduction to Clock Tree Synthesis
9 Introduction to Routing
10 Introduction to Logic Equivalence Checking
11 Introduction to Parasitics and Delay Calculation
12 Introduction to Static Timing Analysis and Timing Optimization
13 Introduction to Signal Integrity
14 Introduction to Power Distribution and IR Drop and Electromigration
15 Introduction to Gate Level Simulation
16 Introduction to Density and Signoff-Checks and Chip finishing
17 Introduction to Low Power Design
18 Introduction to 3D-IC Design and AI Assisted Digital Implementation Flow