The integration of multiple heterogeneous on-package chiplets makes it easier to combine 2D and 2.5D dies from different sources, fabs, designs, and packaging technologies. This on-package mix and match of components for SoC construction is made possible by the Cadence UCIe PHY, Controller, and Verification IP. The Cadence Integrity 3D-IC platform provide designers with the full capability of design planning, implementation, system analysis and signoff to improve PPA, increase performance, and close timing for multi-chiplet designs using advanced or standard packages. Cadence Automotive Solutions