With the advance of the chip process, the scale of digital chips has increased sharply, and the cost of testing has further increased. Advanced DFT technology has been used on large scale SoC chips, including scan path design, JTAG, ATPG (Automatic Test Pattern Generation) and more. However, for some small scale integrated circuits(analog front end chips for example), inserting test circuits, such as scan chains, will increase chip area and add additional power consumption. For this kind of chip, the test pattern generated from functional simulation cases can be used to detect the manufacturing defects and failures. Therefore, there should be some methodology to verify if the coverage has met the goal, especially for automotive chips.We solved this problem using the Cadence Verisium Manage Safety Client, relying on core engines of Xcelium Fault Simulator and the Jasper Functional Safety Verification App (FSV). It provides an credible coverage for ATE (Automated test equipment) pattern.Key words: DFT; Coverage; Verisium Manager; Xcelium fault simulator; Jasper