Interconnect is the key component for any SOC. It works as the core and decide the performance of the SOC. The verification of interconnect faces challenge of verifying correct data routing and performance requirements.This paper is about how to deploy Cadence’ System VIP product to speed up the verification of interconnect. STG(System Testbench Generation) is used for verification environment generation, SVD(System Scoreboard) for data integrity checking and SPA(System Performance Analysis) for performance analysis.With these tools, the verification of interconnect can start right after design is ready. And whenever design is updated, the verification environment can be re-generated in a few minutes. The tool-generated env already have SVD integrated. SPA server will generate performance analysis data in nicely-composed figures.We use a simple 5X5 NIC to try these tools. The NIC requires some customization to work. For example, more constraint added as not all burst types are supported; address translation is required for correct routing. We will also show how these customizations is achieved in the paper.Cadence System VIPs are powerful tool to speed up interconnect verification with user adjustment.