After the JEDEC committees released the DDR5 standard, mainstream DDR5 manufacturers rapidly released their own DDR5 products. However, higher DDR5 rates bring better performance and more challenges in signal integrity design have appeared. Based on the product design simulation case, this paper proposes the DDR5 simulation channel model. With the Sigrity SystemSI(TopXp) tool of the Cadence platform, comprehensively considering the impact of crosstalk, jitters, and noise, risks can be identified and signals can be optimized and improved for the DDR5 design link , effectively supporting the development requirements of the DDR5 design link and facilitating product implementation.