With the continuous improvement of the integration of high-performance computing chips and the advancement of technology, the width of metal wires is getting narrower and narrower, and the voltage drop (IR Drop) will occur on the power network when the resistance on the chip power network increases and the high-density logic gate unit has a logic flip action at the same time, resulting in timing problems in the chip, and even the function failure of the logic gate may occur. Based on the flash PG flow of the Cadence implementation tool Innovus, this paper completes the comprehensive implementation and rapid iteration of the PG network, and uses auto reinforce pg and trim pg to realize the trade-off between the dynamic voltage drop and timing of the high-performance CPU core from two aspects, and completes the whole process optimization for PG network from floorplan to PR (Placement and Route) stage. The results show that under the premise of the same machine resources, flash PG flow can increase the speed of powerplan up to 10 times the original, especially in the design of the top level, which can effectively save the exploration time of PG mesh in the early stage of design. Auto reinforce pg and trim pg repair 48% of the IR Drop violations by reinforcing the pg of the IR weak area and trimming the redundant pg, respectively, and provide more winding resources for the design to achieve the purpose of not deteriorating the timing and DRC (Design Rule Check).